A device includes a photonic cryo die containing photonic components, and an electronic die bonded to the photonic die, the electronic die containing electrically conductive through substrate vias. The electrically conductive through silicon vias can electrically connect a backside redistribution layer to control circuitry for operation in a cryogenic environment in a compact package that exhibits low resistance and low parasitic capacitance.

A device includes a photonic cryo die containing photonic components, and an electronic die bonded to the photonic die, the electronic die containing electrically conductive through substrate vias. The electrically conductive through silicon vias can electrically connect a backside redistribution layer to control circuitry for operation in a cryogenic environment in a compact package that exhibits low resistance and low parasitic capacitance.

A semiconductor device includes a substrate. A semiconductor die is disposed over the substrate. An encapsulant is deposited over the substrate and semiconductor die. A first trench is formed in the encapsulant over the semiconductor die. A second trench is formed completely through the encapsulant and substrate. A conductive layer is formed over the encapsulant and into the first trench and second trench.

A semiconductor device includes a substrate. A semiconductor die is disposed over the substrate. An encapsulant is deposited over the substrate and semiconductor die. A first trench is formed in the encapsulant over the semiconductor die. A second trench is formed completely through the encapsulant and substrate. A conductive layer is formed over the encapsulant and into the first trench and second trench.

Integrated circuit (IC) including domino logic circuit blocks with nFETs that are implemented in a first device layer and pFET keeper transistors that are implemented in a second device layer. The multiple device layers may be integrated within an IC die through layer transfer. Very low temperature operation (e.g., 25 C., or less) may greatly reduce electrical leakage current from dynamic nodes of the domino logic circuit blocks so that output capacitance of the keeper transistors is sufficient to maintain dynamic node charge levels for good noise margin.

The invention relates to a semiconductor device (1) comprising a stack of chips (C1; C) arranged in successive levels along a stacking direction, each chip extending in a main plane perpendicular to the stacking direction. The stack (E) comprises a plurality of chips (C1) of a first type comprising a first portion (P1) and a second portion (P2) each extending in the main plane, the first portion (P1) being liable to release more heat than the second portion (P2) when the chip is operating. Each chip of the first type (C1) is arranged in mechanical contact with a chip in an adjacent level of the stack (E) by way of a stacking surface that extends only over its second portion (P2), such that its first portion (P1) forms a projecting part able to be exposed to a cooling fluid.