An apparatus comprising a first substrate, a dam structure disposed on a first side of the first substrate, and an integrated circuit (IC) memory chip coupled to the first side of the first substrate by a plurality of first conductive members. A second substrate is coupled to a second side of the first substrate by a plurality of second conductive members. A lid coupled to the second substrate encloses the IC memory chip and the first substrate. A thermal interface material (TIM) is coupled between the lid and the dam structure.

A semiconductor package may include a first semiconductor chip extending in a horizontal direction, a first chip stack and a second chip stack, on the first semiconductor chip and horizontally spaced apart from each other, a supporting structure on the first semiconductor chip and interposed between the first and second chip stacks, a first adhesive layer disposed on the first semiconductor chip in contact with the first chip stack and the supporting structure, and a second adhesive layer disposed on the first semiconductor chip in contact with the second chip stack and the supporting structure. Each of the first and second chip stacks may include second semiconductor chips stacked in a vertical direction. Each of the first and second semiconductor chips may include a penetration via. The first and second adhesive layers may be spaced apart from each other with the supporting structure interposed therebetween.

A circuit board according to an embodiment includes an insulating layer; a circuit pattern disposed on the insulating layer, and a first protective layer disposed on the insulating layer, wherein the first protective layer includes a first opening vertically overlapping at least a part of an upper surface of the circuit pattern; wherein an inner wall of the first protective layer constituting the first opening includes: a first portion having a first inclination, and a second portion disposed on the first portion and having a second inclination different from the first inclination, and wherein the first portion overlaps the circuit pattern in a horizontal direction.

A method of forming a back-side power rail device includes forming a device layer over a front-side of a substrate, forming a first interconnect structure over the device layer, the first interconnect structure including a first conductive feature, forming a first dielectric layer over the first interconnect structure, forming a compressive material layer over the first dielectric layer, forming a bonding layer over the first dielectric layer and the compressive material layer, bonding a carrier substrate with the bonding layer, removing, from a back-side of the substrate, at least a portion of the substrate to expose the device layer, forming one or more back-side vias coupled with the device layer opposite the first interconnect structure, forming a second interconnect structure over the device layer and the one or more back-side vias, and forming one or more second conductive features over the second interconnect structure.

In order to achieve the above-described objects, according to an aspect of the present disclosure, a display device includes a substrate which includes an active area and a non-active area extending from the active area and including a pad area and is formed of any one of a transparent conducting oxide and an oxide semiconductor; a plurality of inorganic insulating layers disposed on the substrate; a dam member having one end disposed on the pad area and the other end disposed at the outside of the substrate; and a plurality of flexible films which is disposed to cover the dam member and has one end disposed in the pad area. Accordingly, the dam member which covers the pad area is formed to minimize the crack of the plurality of inorganic insulating layers at the edge of the substrate.

A display device includes a printed circuit board attached to a side of a substrate, a frame facing the printed circuit board, a cover layer disposed between the substrate and the frame and overlapping the printed circuit board in a plan view, and a first reflective layer disposed on a surface of the frame and disposed between the frame and the cover layer.

The disclosure provides an electronic device and a manufacturing method thereof. The electronic device includes a substrate, an electronic element, an underfill layer, and a protective structure. The electronic element is disposed on the substrate. At least a portion of the underfill layer is disposed between the substrate and the electronic element. A thickness of the underfill layer is not greater than a height from a surface of the substrate to an upper surface of the electronic element. The protective structure is disposed on the substrate and adjacent to the underfill layer. The electronic device and the manufacturing method thereof of the disclosure may effectively control an area of the underfill layer.

A method of producing a circuit die where the method includes applying a pre-patterned backing tape to a first surface of a semiconductor substrate that includes the first surface and a second surface, the second surface including one or more circuits; coating the second surface with an encapsulant; removing a patterned portion of the pre-patterned backing tape to expose one or more contact pads on the first surface; applying one of an electrically conductive adhesive (ECA) or solder to the one or more contact pads on the first surface; and coupling an electrical component to the contact pads using the ECA or solder.

Provided is a semiconductor package, the semiconductor package including: a package substrate having an upper surface on which a plurality of bonding pads are arranged; a semiconductor chip disposed on the package substrate, and having an upper surface on which a plurality of chip pads are arranged; an adhesive layer extending onto the upper surface of the package substrate between the semiconductor chip and the package substrate; a dam structure disposed around the adhesive layer, and surrounding a side surface of the adhesive layer; and external connection bumps disposed below the package substrate, and electrically connected to the plurality of bonding pads, wherein the external connection bumps are located below a region covered by the adhesive layer of the package substrate, and an area of the adhesive layer is greater than an area of a region in which the external bumps are disposed.

A semiconductor package includes a package substrate, a plurality of first semiconductor chips stacked on an upper surface of the package substrate in a stair-step configuration, the plurality of first semiconductor chips having an uppermost semiconductor chip at a first height from the upper surface of the package substrate, the uppermost semiconductor chip including a free end portion. Conductive wires respectively electrically connect chip pads of the first semiconductor chips to substrate pads of the package substrate. A plurality of first support structures each have a first end attached to the upper surface of the package substrate and an opposite second end attached to the free end portion of the uppermost semiconductor chip. The first support structures are inclined at an angle relative to the package substrate.