Patent classifications
H10W90/738
SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAME
A semiconductor package may include a first redistribution substrate, a first semiconductor chip and a second semiconductor chip, which are mounted on the first redistribution substrate and are horizontally spaced apart from each other, a first mold layer provided to surround the first and second semiconductor chips and expose bottom surfaces of the first and second semiconductor chips, a bridge chip mounted on the bottom surfaces of the first and second semiconductor chips, a second mold layer provided on the first redistribution substrate to embed the first and second semiconductor chips, the first mold layer, and the bridge chip, a second redistribution substrate disposed on the second mold layer, an upper package mounted on the second redistribution substrate, and a vertical connection structure provided adjacent to the first mold layer to connect the first and second redistribution substrates to each other. The first redistribution substrate may have a recess provided in a top surface of the first redistribution substrate, and the bridge chip may be disposed in the recess.
Integrated circuit packages and methods of forming the same
In an embodiment, a device includes: an integrated circuit die including a die connector; a dielectric layer on the integrated circuit die; an under-bump metallurgy layer having a line portion on the dielectric layer and having a via portion extending through the dielectric layer to contact the die connector; a through via on the line portion of the under-bump metallurgy layer, the through via having a first curved sidewall proximate the die connector, the through via having a second curved sidewall distal the die connector, the first curved sidewall having a longer arc length than the second curved sidewall; and an encapsulant around the through via and the under-bump metallurgy layer.
BONDED STRUCTURES WITH INTEGRATED PASSIVE COMPONENT
In various embodiments, a bonded structure is disclosed. The bonded structure can include an element and a passive electronic component having a first surface bonded to the element and a second surface opposite the first surface. The passive electronic component can comprise a first anode terminal bonded to a corresponding second anode terminal of the element and a first cathode terminal bonded to a corresponding second cathode terminal of the element. The first anode terminal and the first cathode terminal can be disposed on the first surface of the passive electronic component.
IC PACKAGES WITH SUBSTRATES HAVING GLASS CORES WITH LARGE FOOTPRINTS, THIN REDISTRIBUTION LAYERS, AND ELECTRICAL COMPONENTS
An apparatus comprises a first IC die over a substrate comprising a glass core. The glass core comprises a first surface and a second surface opposite the first surface. The first surface comprises an area of at least 5,000 mm.sup.2. A redistribution layer is on the first surface. The redistribution layer comprises a thickness of 100 m or less. An electrical component is within a region of the glass core between the first and second surfaces. A through-glass via extends between the first and second surfaces. A second IC die is over and directly bonded to the first IC die.
NOVEL MICRO BUMP STRUCTURE FOR INTERCONNECTION DIE
A semiconductor device and a method of forming the same are provided. The semiconductor device includes an integrated circuit die, a dielectric layer, an under-bump metallurgy layer, an interconnection die, and a solder material. The integrated circuit die includes a first die connector. The dielectric layer is located on the integrated circuit die. The under-bump metallurgy layer has a line portion on the dielectric layer and a via portion extending through the dielectric layer to contact the first die connector. The interconnection die includes a second die connector. The solder material is located between the line portion of the under-bump metallurgy layer and the second die connector. The under-bump metallurgy layer includes a first copper layer having a uniform grain orientation, wherein the top surface of the first copper layer is in direct contact with the solder material.
POWER MODULE
A power module, can include: a substrate, including an interior having at least one bare die, and a top surface having a first pad; at least one inductor structure disposed on the top surface of the substrate, being configured to electrically connected to the bare die via the first pad, and having a magnetic core; and a thermal conductive structure, including a first portion formed between the top surface of the substrate and a bottom surface of the magnetic core, a second portion extending from the bottom surface of the magnetic core to a top surface of the magnetic core, and a third portion formed on the top surface of the magnetic core, where the first portion, the second portion, and the third portion are connected together.