A display includes a wiring pad and a dummy pad on a first substrate. A first planarization layer is disposed on the wiring pad and the dummy pad. A first pad electrode layer is connected to the wiring pad and a second pad electrode layer is connected to the dummy pad. The first and second pad electrode layers are disposed on the first planarization layer. A first insulating layer covers the first and second pad electrode layers. A first pad electrode upper layer is disposed on the first pad electrode layer. A second pad electrode upper layer is disposed on the second pad electrode layer. The wiring pad, the first pad electrode layer, and the first pad electrode upper layer are electrically connected. The dummy pad, the second pad electrode layer, and the second pad electrode upper layer are electrically connected.

The present disclosure relates to an electronic device comprising a wafer comprising a first upper surface having at least one first contact arranged thereon; and at least one die comprising a second upper surface having at least one second contact arranged thereon, and at least one first lateral surface orthogonal to the second upper surface, said first contact being coupled to said second contact by a connector comprising one first conductive pillar formed on said first contact of said wafer; one second conductive pillar formed on said second contact of said die; and at least one conductive ball positioned in contact with at least a first upper portion of said first pillar(s) and in contact with at least one second upper portion of said second pillar(s).

The present disclosure provides a chip package device. An example chip package device includes: at least one connection pad on a first surface of the chip; at least one pillar extending from, and in contact with, the pad; the pillar being formed in an alloy of a first element and of a second element, a melting temperature of the alloy being greater than a melting temperature of at least one of the first and second elements and greater than 260 C.

The present disclosure relates to a method of bonding column type deposits to a substrate, and more specifically, to a method of bonding to a substrate column type deposits, which are formed in a column shape and connect the substrate and electrodes of a semiconductor chip so as to connect the semiconductor chip to the substrate. A method of bonding column type deposits to a substrate according to the present disclosure has the advantage of bonding the column type deposits having a high aspect ratio to accurate positions while being aligned vertically on the substrate.

Methods of fabricating semiconductor devices and resulting bonded structures. An embodiment method includes tilting a plasma nozzle to an angle with respect to a substrate. The method includes applying, with the plasma nozzle, an oxidation gas onto a first side of at least one substrate-side copper bump on the substrate, forming an oxidized copper sidewall on the first side of the substrate-side copper bump. The method includes bonding a semiconductor chip to the substrate using the substrate-side copper bump.