A semiconductor package includes a package substrate; a semiconductor die vertically stacked on the package substrate; a redistribution layer (RDL) including a dielectric material and metal features that electrically connect the semiconductor die to the package substrate, the RDL having a first Young's modulus; a first underfill layer disposed between the RDL and the semiconductor die; and stress buffers embedded in the RDL below corners of the semiconductor die, each stress buffer having a second Youngs modulus that is at least 30% less than the first Youngs modulus.

A driving substrate, a micro LED transfer device and a micro LED transfer method are provided. A side surface of the driving substrate is arranged with a binding metal layer, a positioning layer is arranged around the binding metal layer, and a width of the positioning layer at a position away from the driving substrate is less than that a width at a position close to the driving substrate.

To improve performance of a semiconductor device. A semiconductor device includes a wiring substrate, a semiconductor chip mounted on a first upper surface of the wiring substrate, an electronic component mounted on the first upper surface, and a stiffener ring fixed to the first upper surface. The stiffener ring includes a first portion arranged to continuously surround a periphery of the semiconductor chip in plan view and adhering to the first upper surface of the wiring substrate, and a second portion connected to the first portion and arranged at a position spaced away from the first upper surface of the wiring substrate in plan view. The second portion of the stiffener ring partially overlaps the electronic component.

A semiconductor package and a method for manufacturing a semiconductor package includes a base substrate including a first surface and a second surface, a first contact pad disposed on the first surface of the base substrate, a first solder resist layer disposed on the first surface of the base substrate, a second solder resist layer covering a portion of an upper surface of the first solder resist layer, and a first connector disposed in the first opening area and the second opening area. The first solder resist layer covers a side surface and a portion of an upper surface of the first contact pad, and defines a first opening area on the first contact pad. The first connector is in contact with the first contact pad. A first width of the first opening area is smaller than a second width of the second opening area.