A semiconductor structure includes a semiconductor substrate, an insulating layer, a conductive feature and an anisotropic conductive structure. The insulating layer is disposed above the semiconductor substrate. The conductive feature is disposed in the insulating layer, wherein a top surface of the conductive feature is adjacent to a top surface of the insulating layer. The anisotropic conductive structure is disposed on the insulating layer and the conductive feature. The anisotropic conductive structure includes a metal oxide porous layer and conductive pillars. The metal oxide porous layer has a first nano-through-hole array exposing the top surface of the conductive feature and a second nano-through-hole array exposing the top surface of the insulating layer. The conductive pillars fill the first nano-through-hole array, wherein the conductive pillars are in contact with the top surface of the conductive feature.

A method for manufacturing a semiconductor device includes providing a semiconductor element having electrode terminals; forming a resist on the semiconductor element, the resist having a first surface facing the electrode terminals and a second surface opposite to the first surface; forming an opening in the resist, which covers the electrode terminals by inserting protrusions of a mold into the resist above the electrode terminals; curing the resist by applying energy to the resist; and widening the opening in a radial direction of the opening. The resist is cured in a state where the second surface of the resist faces an inner surface of the mold with a gap between the second surface of the resist and the inner surface of the mold.

Methods of fabricating semiconductor devices and resulting bonded structures. An embodiment method includes tilting a plasma nozzle to an angle with respect to a substrate. The method includes applying, with the plasma nozzle, an oxidation gas onto a first side of at least one substrate-side copper bump on the substrate, forming an oxidized copper sidewall on the first side of the substrate-side copper bump. The method includes bonding a semiconductor chip to the substrate using the substrate-side copper bump.