Digital-to-analog converter circuit and data driver

Abstract

The present invention includes: a first decoder that outputs mutually different two voltages as first and second selection voltages based on a first bit group of a digital data signal in a first selection state, and outputs one or both of the two voltages as the first and the second selection voltages in a second selection state; a second decoder that outputs mutually different two voltages as third and fourth selection voltages based on a second bit group of the digital data signal in the first selection state and outputs one voltage based on the second bit group as the third and the fourth selection voltages in the second selection state; and an amplifier circuit that averages a combination of the first and the second selection voltages or the third and the fourth selection voltages with predetermined weighting ratios and outputs the averaged voltage.

Claims

1. A digital-to-analog converter circuit comprising: a reference voltage generation circuit that generates a plurality of reference voltages having mutually different voltage values and outputs a first reference voltage group corresponding to a first range and a second reference voltage group corresponding to a second range from the plurality of reference voltages; a first decoder operated according to any one of a plurality of selection states that receives a first bit group in a digital data signal of t (t is an integer of 2 or more) bits, selects mutually different first two reference voltages from the first reference voltage group based on the first bit group and outputs the first two reference voltages as first and second selection voltages when the first decoder is set to a first selection state of the plurality of selection states, the digital data signal including the first bit group and a second bit group; a second decoder operated according to any one of the plurality of selection states that receives the second bit group in the digital data signal, selects mutually different second two reference voltages from the second reference voltage group based on the second bit group and outputs the second two reference voltages as third and fourth selection voltages when the second decoder is set to the first selection state; and an amplifier circuit that outputs a voltage as an output voltage, the voltage being different based on each of the plurality of selection states and obtained by averaging a plurality of voltages with predetermined weighting ratios and amplifying the averaged voltages, the plurality of voltages being each the first selection voltage or the second selection voltage, or the plurality of voltages being each the third selection voltage or the fourth selection voltage.

2. The digital-to-analog converter circuit according to claim 1, wherein the first decoder selects third two reference voltages including an overlap from the first reference voltage group based on the first bit group and outputs the third two reference voltages as the first and the second selection voltages when the first decoder is set to a second selection state of the plurality of selection states, and the second decoder selects one reference voltage from the second reference voltage group based on the second bit group and outputs the one voltage as the third and the fourth selection voltages when the second decoder is set to the second selection state.

3. The digital-to-analog converter circuit according to claim 2, wherein the amplifier circuit includes first to N-th (N is an integer of 2 or more) input terminals, the amplifier circuit receives N selection voltages that are each the first selection voltage or the second selection voltage or N selection voltages that are each the third selection voltage or the fourth selection voltage by the first to N-th input terminals, the amplifier circuit outputs a voltage as the output voltage, and the voltage is obtained by averaging the N selection voltages with a weighting ratio set to each of the first to N-th input terminals and amplifying the averaged voltages, the first decoder supplies the first selection voltage to m (m is positive number of 1 or more) terminals among the first to N-th terminals and supplies the second selection voltage to remaining (N−m) terminals among the first to N-th terminals when the first decoder is set to the first selection state, and the first decoder supplies the first selection voltage or the second selection voltage to each of the first to N-th terminals when the first decoder is set to the second selection state, and the second decoder supplies the third selection voltage to m terminals among the first to N-th terminals and supplies the fourth selection voltage to remaining (N−m) terminals among the first to N-th terminals when the second decoder is set to the first selection state, and the second decoder supplies the third selection voltage or the fourth selection voltage to each of the first to N-th terminals when the second decoder is set to the second selection state.

4. A data driver comprising a digital-to-analog converter unit that receives a video data signal and converts the video data signal into a driving voltage to supply the driving voltage to a display device, the video data signal indicating a luminance level by t (t is an integer of 2 or more) bits including a first bit group and a second bit group, the driving voltage having a voltage value with a magnitude corresponding to the luminance level, wherein the digital-to-analog converter unit includes: a reference voltage generation circuit that generates a plurality of reference voltages having mutually different voltage values and outputs a first reference voltage group corresponding to a first range and a second reference voltage group corresponding to a second range from the plurality of reference voltages; a first decoder operated according to any one of a plurality of selection states that receives a first bit group in a digital data signal of t (t is an integer of 2 or more) bits, selects mutually different first two reference voltages from the first reference voltage group based on the first bit group and outputs the first two reference voltages as first and second selection voltages when the first decoder is set to a first selection state of the plurality of selection states, the digital data signal including the first bit group and a second bit group; a second decoder operated according to any one of the plurality of selection states that receives the second bit group in the digital data signal, selects mutually different second two reference voltages from the second reference voltage group based on the second bit group and outputs the second two reference voltages as third and fourth selection voltages when the second decoder is set to the first selection state; and an amplifier circuit that outputs a voltage as an output voltage, the voltage being different based on each of the plurality of selection states and obtained by averaging a plurality of voltages with predetermined weighting ratios and amplifying the averaged voltages, the plurality of voltages being each the first selection voltage or the second selection voltage, or the plurality of voltages being each the third selection voltage or the fourth selection voltage.

Description

BRIEF DESCRIPTION OF DRAWINGS

(1) FIG. 1A is a circuit diagram illustrating a configuration of an amplifier circuit to perform an interpolation;

(2) FIG. 1B is a drawing illustrating a relationship between N output ports T1 to TN of a decoder circuit, non-inverting input terminals P1 to Px of the amplifier circuit, and weighting ratios;

(3) FIG. 2 is a drawing illustrating an exemplary gamma characteristic curve of a display device;

(4) FIG. 3 is a block diagram illustrating a schematic configuration of a display device 200 that includes a digital-to-analog converter circuit and a data driver according to the present invention;

(5) FIG. 4 is a block diagram illustrating an internal configuration of a data driver 103;

(6) FIG. 5 is a block diagram illustrating an exemplary configuration of the DA converter circuit according to the present invention;

(7) FIG. 6 is a drawing illustrating operations of a first decoder 30 and a second decoder 40 separately for a first selection state and a second selection state;

(8) FIG. 7 is a drawing illustrating exemplary waveforms of third and fourth selection voltages supplied to terminals T1 to TN of an amplifier circuit 20 by the second decoder 40 in each of the first selection state and the second selection state;

(9) FIG. 8 is a drawing schematically illustrating a state of a reference voltage generation circuit 10, and the first decoders 30 and the second decoders 40 which are included in respective converter circuits in a first-period Tc1 in excerpted converter circuits DC1 to DC3;

(10) FIG. 9 is a block diagram illustrating another exemplary configuration of the second decoder 40 included in the converter circuit DC;

(11) FIG. 10A is a drawing illustrating a specification appropriate for a case where the number N of input terminals of the amplifier circuit 20 is N=2;

(12) FIG. 10B is a drawing illustrating a specification appropriate for a case where the number N of input terminals of the amplifier circuit 20 is N=3;

(13) FIG. 11A is a drawing illustrating an exemplary operation configuration of the second decoder 40 illustrated in FIG. 9 in the first selection state;

(14) FIG. 11B is a drawing illustrating an exemplary operation configuration of the second decoder 40 illustrated in FIG. 9 in the second selection state;

(15) FIG. 12 is a circuit diagram illustrating an exemplary internal configuration of a second sub-decoder 42A as another embodiment of a second sub-decoder 42;

(16) FIG. 13A is a diagram illustrating another exemplary operation configuration of the second decoder 40 illustrated in FIG. 9 in the first selection state;

(17) FIG. 13B is a diagram illustrating another exemplary operation configuration of the second decoder 40 illustrated in FIG. 9 in the second selection state;

(18) FIG. 14 is a circuit diagram illustrating an exemplary internal configuration of a second sub-decoder 42B as another embodiment of the second sub-decoder 42;

(19) FIG. 15 is a circuit diagram illustrating a configuration of an output unit that outputs selection voltages of levels 0 to 7 illustrated in FIG. 10A and FIG. 10B in the first sub-decoder 41;

(20) FIG. 16A is a circuit diagram illustrating a configuration of a filter circuit 43 when the number of the input terminals of the amplifier circuit 20 is two; and

(21) FIG. 16B is a circuit diagram illustrating a configuration of the filter circuit 43 when the number of the input terminals of the amplifier circuit 20 is three.

DETAILED DESCRIPTION

(22) FIG. 3 is a block diagram illustrating a schematic configuration of a display device 200 that includes a digital-to-analog converter circuit and a data driver according to the present invention.

(23) As illustrated in FIG. 3, the display device 200 includes a display panel 100, a drive controller 101, a scanning driver 102, and a data driver 103.

(24) The display panel 100 includes, for example, a liquid crystal panel or an organic EL panel, and includes r (r is a natural number of 2 or more) horizontal scanning lines S1 to Sr extending in a horizontal direction of a two-dimensional screen, and n (n is a natural number of 2 or more) data lines D1 to Dn extending in a vertical direction of the two-dimensional screen. Display cells serving as pixels are formed on respective intersecting portions of the horizontal scanning lines and the data lines.

(25) The drive controller 101 supplies the scanning driver 102 with a scan timing signal to generate a horizontal scanning pulse supplied to each of the scanning lines.

(26) The drive controller 101 generates various control signals including a start pulse signal STP, a clock signal CLK, and control signals CTL and XCTL, and a video digital signal DVS based on a video signal VD to supply them to the data driver 103.

(27) The scanning driver 102 applies the horizontal scanning pulse in order to each of the horizontal scanning lines S1 to Sr of the display panel 100 based on the scan timing signal supplied from the drive controller 101.

(28) The data driver 103 acquires a series of video data PD, which is included in the video digital signal DVS and individually indicates a luminance level of each pixel in, for example, 8 bits, corresponding to the various control signals (STP, CLK, CTL, and XCTL) supplied from the drive controller 101. The number of bits of the video data PD is not limited to 8 bits. Then, the data driver 103 converts the acquired series of video data PD into n driving voltages G1 to Gn having voltage values with magnitudes corresponding to the luminance levels indicated by the respective pieces of the video data PD for every (n) horizontal scanning line, and supply them to the respective data lines D1 to Dn of the display panel 100.

(29) FIG. 4 is a block diagram illustrating an internal configuration of the data driver 103.

(30) As illustrated in FIG. 4, the data driver 103 includes a shift register 50, a data register latch 60, a level shifter 70, and a digital to analog (DA) converter 80.

(31) The shift register 50 generates latch timing signals U1 to Un for selecting a latch in synchronization with the clock signal CLK corresponding to the start pulse STP supplied from the drive controller 101, and supplies them to the data register latch 60.

(32) The data register latch 60 sequentially acquires the video data PD supplied from the drive controller 101 based on the latch timing signals U1 to Un, and supplies video data signals R1 to Rn indicating the respective pieces of the video data PD to the level shifter 70 for every (n) horizontal scanning lines.

(33) The level shifter 70 performs level shift processing to increase the signal level to each of the video data signals R1 to Rn, and supplies obtained n pieces of video data signal J1 to Jn to the DA converter 80.

(34) The DA converter 80 receives each of the video data signals J1 to Jn as the digital data signals based on the control signals CTL and CTLX, converts the video data signals J1 to Jn to driving voltages G1 to Gn having analog voltage values, respectively, and outputs them.

(35) As illustrated in FIG. 4, the DA converter 80 includes a reference voltage generation circuit 10 and converter circuits DC1 to DCn.

(36) The reference voltage generation circuit 10 generates a plurality of reference voltages having mutually different voltage values, and outputs a first reference voltage group VX corresponding to a first range (for example, a range B of FIG. 2) and a second reference voltage group VZ corresponding to a second range (for example, a range A of FIG. 2) among the plurality of reference voltages. The reference voltage generation circuit 10 supplies the output first reference voltage group VX and the second reference voltage group VZ to each of the converter circuits DC1 to DCn.

(37) The converter circuits DC1 to DCn receive the first reference voltage group VX, the second reference voltage group VZ, and the control signals CTL and CTLX, and individually receive the video data signals J1 to Jn, respectively. The converter circuits DC1 to DCn select the reference voltages corresponding to the video data signals J1 to Jn for each video data signal based on the control signals CTL and CTLX from the first reference voltage group VX and the second reference voltage group VZ. The converter circuits DC1 to DCn output the reference voltages that they have selected as driving voltages G1 to Gn, respectively. Note that, as illustrated in FIG. 4, the converter circuits DC1 to DCn are disposed corresponding to the video data signals J1 to Jn, respectively, and have the same internal configuration.

Example 1

(38) FIG. 5 is a block diagram illustrating a configuration of a digital-to-analog converter circuit (also referred to as a DA converter circuit) of a RDAC system according to the present invention that includes the converter circuit DC1 and the reference voltage generation circuit 10 extracting the converter circuit DC1 among the converter circuits DC1 to DCn illustrated in FIG. 4.

(39) The reference voltage generation circuit 10 includes a ladder resistor LDR that receives, for example, a predetermined electric potential VGH and an electric potential VGL lower than the electric potential VGH, and divides a voltage between the electric potentials VGH and VGL into a plurality of voltages having mutually different voltage values. The reference voltage generation circuit 10 classifies the plurality of divided voltages divided by the ladder resistor LDR as follows, thus generating the first reference voltage group VX and the second reference voltage group VZ.

(40) A plurality of reference voltages belonging to the first reference voltage group VX are included in a voltage range Vup of the driving voltage corresponding to the gradation levels of the range B where the change of the driving voltage relative to the change of the gradation level has a linear characteristic for each predetermined gradation level range as illustrated in FIG. 2. The plurality of reference voltages belonging to the first reference voltage group VX have relatively small differences between the voltage values corresponding to the respective adjacent gradation levels, and included in the voltage range applicable to the interpolation performed in the amplifier circuit 20 described later.

(41) A plurality of reference voltages belonging to the second reference voltage group VZ are included in a voltage range Vdw of the driving voltage corresponding to the gradation levels of the range A where the change of the driving voltage relative to the change of the gradation level has a nonlinear characteristic as illustrated in FIG. 2. The plurality of reference voltages belonging to the second reference voltage group VZ includes the reference voltages that have relatively large differences between the voltage values corresponding to the respective adjacent gradation levels. Therefore, the plurality of reference voltages belonging to the second reference voltage group VZ are included in the voltage range inappropriate for the interpolation performed in the amplifier circuit 20.

(42) The converter circuit DC1 includes the amplifier circuit 20, a first decoder 30, and a second decoder 40.

(43) Both the first decoder 30 and the second decoder 40 receive the control signals (CTL, XCTL) that instruct a setting to one of the first selection state and the second selection state. Accordingly, the first decoder 30 and the second decoder 40 are each set to the first selection state when the control signals (CTL, XCTL) instruct the first selection state, and set to the second selection state when the control signals (CTL, XCTL) instruct the second selection state. Furthermore, the first decoder 30 and the second decoder 40 receive, for example, the video data signal J1 as the digital data signal of, for example, 8 bits.

(44) When being set to the first selection state, the first decoder 30 selects mutually different two reference voltages VA and VB from the first reference voltage group VX based on a first bit signal group BT1 corresponding to the first range of the video data signal (J1). The first decoder 30 outputs the selected two reference voltages VA and VB as respective first and second selection voltages.

(45) When being set to the second selection state, the first decoder 30 selects the two reference voltages VA and VB including an overlap from the first reference voltage group VX based on the first bit signal group BT1 described above. Here, when the same two reference voltages VA (or VB) are selected, the first decoder 30 outputs the same reference voltages as the first and the second selection voltages. Meanwhile, when the mutually different two reference voltages VA and VB are selected, the first decoder 30 outputs the selected two reference voltages VA and VB as the respective first and the second selection voltages.

(46) The first decoder 30 supplies the above-described first and second selection voltages to the amplifier circuit 20.

(47) When being set to the first selection state, the second decoder 40 selects mutually different two reference voltages VC and VD from the second reference voltage group VZ based on a second bit signal group BT2 corresponding to the second range of the video data signal J1. Then, the second decoder 40 outputs the selected two reference voltages VC and VD as respective third and fourth selection voltages.

(48) When being set to the second selection state, the second decoder 40 selects the same two reference voltages VC (or VD) from the second reference voltage group VZ based on the above-described second bit signal group BT2, and the second decoder 40 outputs the same reference voltages as the third and the fourth selection voltages.

(49) The second decoder 40 supplies the above-described third and fourth selection voltages to the amplifier circuit 20.

(50) The above-described selection voltages VA and VB are preferably a combination of the voltage values adjacent to one another or the voltages having a small difference in voltage value in the first reference voltage group VX. Similarly, the selection voltages VC and VD are preferably a combination of the voltage values adjacent to one another in the second reference voltage group VZ.

(51) The amplifier circuit 20 includes a differential amplifier (operational amplifier) that includes first to N-th terminals T1 to TN (N is an integer of 2 or more) as the non-inverting input terminals and performs the interpolation. For example, the amplifier circuit of FIG. 1A can be used.

(52) The amplifier circuit 20 averages and amplifies N voltages that are each the first selection voltage or the second selection voltage or N voltages that are each the third selection voltage or the fourth selection voltage received by the terminals T1 to TN with the weighting ratios preliminarily set to the respective terminals T1 to TN, and outputs the amplified voltage as the output voltage Vout. The amplifier circuit 20 included in the converter circuit DC1 outputs the output voltage Vout as a driving voltage G1.

(53) In the first selection state described above, the first decoder 30 supplies the above-described first selection voltages (VA) tom (m is an integer of 1 or more) terminal among the terminals T1 to TN of the amplifier circuit 20, and supplies the second selection voltages (VB) to remaining (N−m) terminals. In the second selection state described above, the first decoder 30 supplies the first selection voltage or the second selection voltage (VA or VB) described above to each of the terminals T1 to TN of the amplifier circuit 20. Note that, the second selection state includes a case where the same reference voltages (only one of VA or VB) are supplied to each of the terminals T1 to TN of the amplifier circuit 20 from the first decoder 30.

(54) In the first selection state, the second decoder 40 supplies the above-described third selection voltage (VC) to m terminals among the terminals T1 to TN of the amplifier circuit 20, and supplies the fourth selection voltage (VD) to remaining (N−m) terminals. In the second selection state, the second decoder 40 supplies the third selection voltage and the fourth selection voltage including the same reference voltages (only one of VC or VD) to each of the terminals T1 to TN of the amplifier circuit 20.

(55) That is, to the terminals T1 to TN of the amplifier circuit 20, a first voltage wiring group LV1 that transmits the first and the second selection voltages output from the first decoder 30 and a second voltage wiring group LV2 that transmits the third and the fourth selection voltages output from the second decoder 40 are commonly connected.

(56) The following describes respective operations of the first decoder 30 and the second decoder 40 illustrated in FIG. 5.

(57) FIG. 6 is a drawing illustrating the operation of the first decoder 30 by the first bit signal group BT1 in the video data signal J1 and the operation of the second decoder 40 by the second bit signal group BT2 separately for the first selection state and the second selection state.

(58) In FIG. 6, assume that the control signals (CTL, XCTL) specify the first selection state in the case of, for example, CTL=0 (low level in logical value), and specifies the second selection state in the case of CTL=1 (high level in logical value). The control signal XCTL is a complementary signal of the control signal CTL. The number N of the input terminals of the amplifier circuit 20 and above-described “m” are assumed to m≥1 and N≥2, and the selection voltage is assumed to VA≠VB and VC≠VD.

(59) In the first selection state (CTL=0), the first decoder 30 selects the two different reference voltages VA and VB without an overlap as the first selection voltage VA and the second selection voltage VB from the first reference voltage group VX based on the first bit signal group BT1. The first decoder 30 supplies the first selection voltage VA to m terminals among the terminals T1 to TN of the amplifier circuit 20 and supplies the second selection voltage VB to remaining (N−m) terminals among the terminals T1 to TN.

(60) In the second selection state (CTL=1), the first decoder 30 selects the two reference voltages including an overlap, the voltage VA or VB as the first selection voltage and the voltage VA or VB as the second selection voltage, from the first reference voltage group VX based on the first bit signal group BT1. The first decoder 30 supplies the voltage VA or VB to each of the terminals T1 to TN of the amplifier circuit 20. At this time, the first decoder 30 may selectively supply the voltages VA and VB in mixture to the respective terminals T1 to TN, or may supply only one of the voltages VA and VB to each of the terminals T1 to TN.

(61) In the first selection state (CTL=0), the second decoder 40 selects the two different reference voltages VC and VD without an overlap, the voltage VC as the third selection voltage and the voltage VD as the fourth selection voltage, from the second reference voltage group VZ based on the second bit signal group BT2. The second decoder 40 supplies the third selection voltage VC tom (m is an integer of 1 or more) terminals among the terminals T1 to TN of the amplifier circuit 20 and supplies the fourth selection voltage VD to remaining (N−m) terminals among the terminals T1 to TN.

(62) In the second selection state (CTL=1), the second decoder 40 selects the same reference voltages, the voltage VC or VD as the third selection voltage and the voltage (VC or VD) same as the third selection voltage as the fourth selection voltage, from the second reference voltage group VZ based on the second bit signal group BT2. The second decoder 40 supplies only one of the voltages VC and VD to every terminal of the terminals T1 to TN.

(63) FIG. 7 is a drawing illustrating exemplary waveforms of the third and the fourth selection voltages supplied to the terminals T1 to TN of the amplifier circuit 20 by the second decoder 40 in each of the first selection state and the second selection state specified by the control signals (CTL, XCTL) in the configuration illustrated in FIG. 5. FIG. 7 illustrates one data period after a reception of the bit signal groups (BT1, BT2) of the video data signal for one pixel by the amplifier circuit 20 until the output of the selection voltage.

(64) As illustrated in FIG. 7, the one data period includes a first-period Tc1 and a second-period Tc2 following the first-period Tc1. In the first-period Tc1, the control signal (CTL, XCTL) is CTL=0 (low level: L), and correspondently, the second decoder 40 is set to the first selection state. In the second-period Tc2, the control signal (CTL, XCTL) is CTL=1 (high level: H), and correspondently, the second decoder 40 is set to the second selection state. Since the control signal XCTL is a complementary signal of the control signal CTL, the description will be omitted.

(65) In FIG. 7, solid line waveforms W1 and W2 in the first-period Tc1 are output waveforms of the selection voltages in the first selection state output from the second decoder 40. A dashed line waveform W3 illustrates an output waveform of a conventional decoder, that is, a decoder that keeps the second selection state over the one data period. FIG. 7 illustrates the example of the worst case where all of the n outputs of the data driver perform the same operation in the one data period where the selection voltage is switched from a maximum selection voltage VrM to a minimum selection voltage Vr0a.

(66) The dashed line waveform W3 illustrates the change from the selection voltage VrM selected in the previous one data period to the selection voltage Vr0a in the one data period. The conventional decoder selects the selection voltage Vr0a over the one data period and supplies the selection voltage Vr0a to the terminals T1 to TN of the amplifier circuit 20. The speed of the voltage change of the dashed line waveform W3 depends on a time constant with a resistance of the wiring transmitting the selection voltage Vr0a and an impedance of the decoder itself having an input capacitance (gate parasitic capacitance of the differential pair transistors) of the amplifier circuit as a load.

(67) In this example, in the first-period Tc1 immediately after the start of the one data period, the second decoder 40 is set to the first selection state (CTL=0), and the different two selection voltages (VC, VD)=(Vr0a, Vr0b) are selected as the third and the fourth selection voltages. The selection voltage Vr0b is configured to be, for example, a voltage adjacent to the selection voltage Vr0a, namely for example, a voltage higher than Vr0a by only one stage. The second decoder 40 outputs the selection voltage Vr0a to m terminals among the terminals T1 to TN of the amplifier circuit 20, and supplies the selection voltage Vr0b to (N−m) terminals among the terminals T1 to TN. The solid line waveforms W1 and W2 of the terminals supplied with the selection voltages Vr0a and Vr0b, respectively, indicate the voltage change faster than that of the dashed line waveform W3 caused by decrease of the input capacitance of the amplifier circuit 20 connected to one reference voltage line. The terminals T1 to TN of the amplifier circuit 20 have the predetermined weighting ratios, and the amplifier circuit 20 outputs the voltage between the selection voltages Vr0a and Vr0b, that is, weighted average voltages corresponding to the weighting ratios. As the weighting ratios of the selection voltage Vr0a to Vr0b approaches 1:1, the voltage changes of the waveforms W1 and W2 become close to equivalent, and the voltage changes become fast.

(68) In the second-period Tc2, the second decoder 40 is set to the second selection state (CTL=1), and the selection voltage Vr0a corresponding to the digital signal group is selected as the third and the fourth selection voltages. The second decoder 40 supplies the selection voltage Vr0a to the terminals T1 to TN. For the terminal supplied with the selection voltage Vr0b in the first-period Tc1, while being switched to the supply of the selection voltage Vr0a, the switching is promptly performed because of a small electric potential difference between the selection voltages Vr0a and Vr0b. The selection voltage Vr0a is input to the amplifier circuit 20, and the amplifier circuit 20 amplifies the selection voltage Vr0a and outputs the amplified selection voltage Vr0a.

(69) As described above, this example indicates the example where the one data period is divided into the first-period Tc1 in the first selection state and the second-period Tc2 in the second selection state by the control signals (CTL, XCTL).

(70) In the first selection state (Tc1), the decoders (30, 40) supply selection voltage groups having mutually different voltage values to the amplifier circuit 20. Meanwhile, in the second selection state (Tc2), the decoders supply selection voltage groups having the same voltage value or the mutually different voltage values based on the digital data signal (J1) to the amplifier circuit 20. Accordingly, the change of the input voltage in the amplifier circuit 20 can be accelerated, and in accordance with this, the change speed of the output voltage of the amplifier circuit 20 can be increased. By performing the similar control to every gradation level, the change speeds of the output voltage of the amplifier circuit 20 in the respective gradation levels can be made same.

(71) The following describes the effects of the data driver 103 that includes the converter circuits DC1 to DCn configured as illustrated in FIG. 5 with an example where the number N of the input terminals of the amplifier circuit 20 and the above-described “m” are assumed to N=2 and m=1, respectively, with reference to FIG. 8.

(72) FIG. 8 is a drawing schematically illustrating a state of the amplifier circuits 20, the first decoders 30, and the second decoders 40, which are included in the respective converter circuits DC1 to DC3 excerpted from the converter circuits DC1 to DCn, and the reference voltage generation circuits 10 in the first-period Tc1.

(73) In the first-period Tc1, the first decoders 30 and the second decoders 40 of the respective converter circuits DC are set to the first selection state. In the example illustrated in FIG. 8, in the first-period Tc1, the second decoders 40 supply the two different selection voltages Vr0a and Vr0b having a small electric potential difference therebetween to the plurality of input terminals of the respective n amplifier circuits 20 corresponding to all the outputs of the data driver 103. A wiring LV2a to which parasitic capacitances Cp1 of the respective input terminals, which receive the selection voltage Vr0a, of the amplifier circuits 20 are connected is a wiring different from a wiring LV2b to which parasitic capacitances Cp2 of the respective input terminals, which receive the selection voltage Vr0b, are connected, that is, the wiring LV2a and the wiring LV2b are wirings not electrically connected to one another. Accordingly, the parasitic capacitances connected to the respective wirings LV2a and LV2b are decreased compared with the case where, in the first-period Tc1, the wiring LV2a or LV2b is connected to both the parasitic capacitances Cp1 and Cp2 parasitized to the respective input terminals of all the amplifier circuits as the conventional decoder, thus increasing the speed of the voltage change of each input terminal in accordance with the decrease. When the voltages received by the input terminals of the respective amplifier circuits sufficiently approach the selection voltages Vr0a, Vr0b in the first-period Tc1, the operation state is returned to the operation state similar to that of the conventional decoder in the second-period Tc2.

(74) Accordingly, even in the worst case where all the input terminals of the n amplifier circuits 20 corresponding to all the outputs are connected to one of the wirings LV2a and LV2b in the second-period Tc2, the change of the input voltage of the amplifier circuit in the one data period can be accelerated. The change speeds of the input voltage of the amplifier circuit in the respective gradation levels can be made same. Consequently, the change of the output voltage of the amplifier circuit can be accelerated to make the speed of the change of the output voltage between the gradations uniform.

Example 2

(75) FIG. 9 is a block diagram illustrating another exemplary configuration of the second decoder 40 included in the converter circuit DC. In FIG. 9, since the reference voltage generation circuit 10, the amplifier circuit 20, and the first decoder 30 included in the DA converter circuit are same as those illustrated in FIG. 5, descriptions for them are omitted.

(76) In the configuration illustrated in FIG. 9, the second bit signal group BT2 is further divided into a first sub-bit signal group b1, a second sub-bit signal group b2, and a third sub-bit signal group b3.

(77) Furthermore, in the configuration illustrated in FIG. 9, the second decoder 40 includes a first sub-decoder 41 that receives the first sub-bit signal group b1 and a second sub-decoder 42 that receives the second sub-bit signal group b2.

(78) The first sub-decoder 41 selects two different selection voltages (VC, VD) without an overlap from the second reference voltage group VZ corresponding to the first sub-bit signal group b1. The first sub-bit signal group b1 includes, for example, a high-order bit group including a most significant bit.

(79) The second sub-decoder 42 selects third and fourth selection voltages including an overlap from the two selection voltages having different voltage values based on the second sub-bit signal group b2 corresponding to the control signals (CTL, XCTL), and supply them to the terminals T1 to TN of the amplifier circuit 20. The second sub-bit signal group b2 includes, for example, a low-order bit group including a least significant bit.

(80) The second decoder 40 may employ a configuration where a filter circuit 43 configured to reduce occurrence of an output short circuit between the first decoder 30 and the second decoder 40 is disposed at a subsequent stage of the second sub-decoder 42. The filter circuit 43 cuts off between an output port of the second sub-decoder 42 and the terminals T1 to TN of the amplifier circuit 20 when a voltage within a selection voltage range (for example, Vup of FIG. 2) assigned to the first decoder 30 is output based on the third sub-bit signal group b3 (for example, including the most significant bit) that specifies the range of the selection voltage. When a voltage within a selection voltage range (for example, Vdw of FIG. 2) assigned to the second decoder 40 is output, the filter circuit 43 conducts electricity between the output port of the second sub-decoder 42 and the terminals T1 to TN of the amplifier circuit 20.

(81) The first sub-decoder 41 may employ a configuration where the first sub-decoder 41 selects two different selection voltages (VC, VD) and outputs them via its own terminals TC and TD. The second sub-decoder 42 employs a configuration where the second sub-decoder 42 receives the selection voltages (VC, VD) of the terminals TC and TD of the first sub-decoder 41 and outputs them via terminals Q1 to QN as output ports. The filter circuit 43 may include a switch group that controls conduction/cutoff between the terminals Q1 to QN of the second sub-decoder 42 and the terminals T1 to TN of the amplifier circuit 20 in one-to-one. The filter circuit 43 may be disposed in the second decoder 40 as illustrated in FIG. 9 or may be disposed in the first decoder 30.

Example 3

(82) FIG. 10A and FIG. 10B are drawings illustrating exemplary operations of the decoders (30, 40) in the above-described second selection state (Tc2) as examples of appropriate specifications for the DA converter circuits (10, DC1) according to the present invention.

(83) FIG. 10A is a drawing illustrating a specification appropriate for a case where the number N of input terminals of the amplifier circuit 20 is N=2, and FIG. 10B illustrates the case of N=3. FIG. 10A and FIG. 10B each illustrate a relationship among the reference voltage Vref selected by the first decoder 30 and the second decoder 40, bit codes (bits D4 to D0) of the data signal, and the selection voltages [V(T1) to V(TN)] input to the terminals T1 to TN of the amplifier circuit 20 in the matching with respective levels indicating the voltage values of the output voltage in stages. The levels 0 to 7 illustrated in FIG. 10A and FIG. 10B correspond to the voltage in the range A, which is inappropriate for the interpolation, of the gamma characteristic curve of FIG. 2, and the level 8 or more corresponds to the voltage in the range B, which is appropriate for the interpolation, of the gamma characteristic curve of FIG. 2. The levels between the adjacent two reference voltages (Vref) in the range B have a linear characteristic by the interpolation of the amplifier circuit. While FIG. 10A and FIG. 10B illustrate the levels to the level 15 and the level 23 for convenience of the drawings, the levels can be further expanded. Extension of the number of levels also increases the number of bits of the corresponding digital data signal.

(84) As illustrated in FIG. 10A and FIG. 10B, when the output voltage is in the range of the levels 0 to 7 at the end of the one data period, the decoder selects the reference voltages having the same voltage value, and supplies the respective reference voltages to the terminals T1 to TN of the amplifier circuit 20 as the selection voltages [V(T1) to V(TN)]. However, while being set to the above-described first selection state (Tc1), the decoder selects the reference voltage corresponding to the level and the reference voltage having the voltage value higher or lower than that of the corresponding reference voltage by only one stage for each level, and supplies the respective reference voltages to the terminals T1 to TN of the amplifier circuit 20 as the selection voltages [V(T1) to V(TN)].

(85) In the specification of FIG. 10A, when the output voltage is the level 8 or more, the decoder selects the same reference voltage for every two stages (for example, the levels 8, 10, 12) as the selection voltages V(T1) and V(T2) supplied to the terminals T1 and T2 of the amplifier circuit 20. For the levels between the levels of every two stages (for example, the levels 9, 11), the decoder selects the two reference voltages selected for the respective two levels adjacent to upper and lower of the level, and outputs them as the selection voltages V(T1) and V(T2). However, while being set to the above-described first selection state (Tc1), the decoder selects the reference voltage corresponding to the level and the reference voltage having the voltage value higher or lower than that of the corresponding reference voltage by only one stage for each level, and supplies the respective reference voltages to the terminals T1 to T2 of the amplifier circuit 20 as the selection voltages [V(T1) to V(T2)].

(86) In the specification of FIG. 10B, when the output voltage is the level 8 or more, the decoder selects the same reference voltage for every four stages (for example, the levels 8, 12, 16) as the selection voltages V(T1) to V(T3) supplied to the terminals T1 to T3 of the amplifier circuit 20 at the end of the one data period. For the levels between the levels of every four stages (for example, the levels 9 to 11, the levels 13 to 15), the decoder selects the two reference voltages selected for the respective two levels adjacent to upper and lower of the level, assigns the two reference voltages to the selection voltages V(T1) to V(T3) corresponding to the bit codes, and outputs them. However, while being set to the above-described first selection state (Tc1), the decoder selects the reference voltage corresponding to the level and the reference voltage having the voltage value higher or lower than that of the corresponding reference voltage by only one stage for each level, assigns the respective reference voltages to the selection voltages [V(T1) to V(T3)] at a predetermined ratio, and supplies them to the terminals T1 to T3 of the amplifier circuit 20.

(87) While in the example described above, the reference voltages selected by the decoder while the decoder is set to the first selection state (Tc1) are the reference voltage corresponding to the level of the output voltage and the reference voltage having the voltage value closest to that of the corresponding reference voltage, the reference voltage is not limited to this.

(88) For example, when the voltage (a present output voltage) output from the amplifier circuit 20 in the present one data period is lower than the voltage (referred to as a previous output voltage) output from the amplifier circuit 20 in the immediately before one data period, the decoder only needs to select the mutually different two reference voltages lower than the previous output voltage over the period where the decoder is set to the first selection state. When the present output voltage is higher than the above-described previous output voltage, the decoder only needs to select the mutually different two reference voltages higher than the previous output voltage over the period where the decoder is set to the first selection state.

(89) In the conventional decoder configuration, in the worst case where the input terminals of the amplifier circuit 20 for all the output are connected to the same wiring, the impedance of the wiring becomes maximum, the voltage changes at the respective inputs of the amplifier circuit 20 are delayed most, thus causing the delay of the change speed of the output voltage of the amplifier circuit 20 in some cases. As illustrated in FIG. 10A and FIG. 10B, the range B includes the gradation levels (for example, even number levels of FIG. 10A) where the input terminals of the amplifier circuit 20 are connected to the same reference voltage wiring, and the gradation levels (for example, odd number levels of FIG. 10A) where the input terminals of the amplifier circuit 20 are connected to the different reference voltage wirings. That is, the impedance of the wiring differs depending on the gradation level to cause the difference between the levels in the speed of the voltage change of each input terminal of the amplifier circuit 20. The difference between the levels in the speed of the voltage change also influences luminance characteristics of the display device corresponding to the gradation level to cause the degradation of the display quality.

(90) In the present invention, by the control where the decoder is switched from the first selection state (first-period Tc1) to the second selection state in the one data period, the voltage change of each input terminal of the amplifier circuit 20 can be accelerated in the first-period Tc1. Accordingly, the present invention can accelerate the change speed of the output voltage of the amplifier circuit 20. In the specifications illustrated in FIG. 10A and FIG. 10B, in the first-period Tc1, at all of the gradation levels in the range A and the range B, the respective input terminals of the amplifier circuit 20 are connected to the different reference voltage wirings, thus reducing the difference between the levels in the speed of the voltage change of each input terminal of the amplifier circuit 20. Accordingly, the degradation of the display quality can be suppressed.

(91) The number N of the input terminals of the amplifier circuit 20 can be expanded. For example, the extension of the specification can be made such that the number N of the terminals is N=4, the weighting ratio of the four terminals T1, T2, T3, and T4 is 1:1:2:4, and the output voltage Vout is Vout=[V(T1)+V(T2)+2×V(T3)+4×V(T4)]/8. In the specification in this case, in the range A, the reference voltage is configured for each gradation level, and the same reference voltage is supplied to the four input terminals of the amplifier circuit 20. In the range B, the reference voltage is configured for every eight levels, and the different two reference voltages are assigned and supplied to the four input terminals of the amplifier circuit 20 corresponding to the bit codes. So, the present invention can also accelerate the change speed of the output voltage of the amplifier circuit 20 with the number N of the input terminals as described above, by the control where the decoder is switched from the first selection state (first-period Tc1) to the second selection state in the one data period.

Example 4

(92) FIG. 11A and FIG. 11B are drawings illustrating exemplary operation configurations in the first selection state and the second selection state by the second decoder 40 illustrated in FIG. 9 when the amplifier circuit 20 includes the two terminals T1 and T2 as the input terminals.

(93) Assume that the DA converter circuit illustrated in FIG. 9 outputs the selection voltages in eight stages of the levels 0 to 7 illustrated in FIG. 10A. This range of the selection voltage is equivalent to, for example, the voltage range Vdw corresponding to the range A, which has the nonlinear characteristic, of the gamma characteristic curve illustrated in FIG. 2. The second sub-decoder 42 receives the two different reference voltages VC and VD selected by the first sub-decoder 41, and controls the selection voltages supplied to the terminals T1 and T2 of the amplifier circuit 20 based on the control signal CTL and the bit D0 as the least significant bit in the digital data signal (J1). The description of the complementary signals XCTL and XD0 of the control signal CTL and the bit D0 are omitted. The weighting ratio of the two terminals T1, T2 of the amplifier circuit 20 is assumed to be set to 1:1.

(94) When being set to the first selection state corresponding to the control signal CTL=0 (low level), the second sub-decoder 42 supplies the mutually different two selection voltages VC and VD to the terminals T1 and T2 of the amplifier circuit 20, respectively as illustrated in FIG. 11A irrespective of the value of the bit D0. At this time, the amplifier circuit 20 receives the selection voltages (VC, VD) at the terminals T1 and T2 with the weighting ratio of 1:1, and outputs the voltage (VC+VD)/2 as the weighted average corresponding to the weighting ratio. Accordingly, in the first selection state, the voltage changes of the terminals T1, T2 are promptly performed.

(95) When being set to the second selection state corresponding to the control signal CTL=1 (high level), the second sub-decoder 42 supplies only the selection voltage VC among the selection voltages VC and VD to each of the terminals T1 and T2 of the amplifier circuit 20 as illustrated in FIG. 11B corresponding to the bit D0=0. The amplifier circuit 20 outputs the voltage VC. Corresponding to the bit D0=1, the second sub-decoder 42 supplies only the selection voltage VD among the selection voltages VC and VD to each of the terminals T1 and T2 of the amplifier circuit 20. The amplifier circuit 20 outputs the voltage VD.

(96) As described above, the first-period Tc1 in the first selection state and the second-period Tc2 in the second selection state are provided in the one data period where the voltage output corresponding to the digital data signal (J1) is performed, and in the first-period Tc1, the voltage change of each input terminal of the amplifier circuit 20 is accelerated even when the voltage change is large. That is, in the initial first-period Tc1, processing to increase the change speed of the output voltage of the amplifier circuit 20 is performed to the voltage corresponding to the digital data signal or the voltage at the proximity of the corresponding voltage, and in the subsequent second-period Tc2, driving is stabilized at the voltage corresponding to the digital data signal.

(97) FIG. 12 is a circuit diagram illustrating an exemplary internal configuration of a second sub-decoder 42A configured as the second sub-decoder 42 along the specifications of FIG. 11A and FIG. 11B. The second sub-decoder 42A includes terminals TC and TD that receive mutually different selection voltages VC and VD, Nch transistor switches SW1 to SW8, and terminals Q1 and Q2. A filter circuit 43A is disposed between the terminals Q1 and Q2 and the terminals T1 and T2 of the amplifier circuit 20.

(98) The switch SW1 becomes ON state in the case of the control signal CTL=1 (high level), and supplies the selection voltage VD received by the terminal TD to the switch SW2.

(99) The switch SW2 becomes ON state in the case of the bit D0=1 (high level), and supplies the selection voltage VD supplied from the switch SW1 to the terminal T1 of the amplifier circuit 20 via the terminal Q1 and the filter circuit 43A.

(100) The switch SW3 becomes ON state in the case of the control signal CTL=1 (high level), and supplies the selection voltage VC received by the terminal TC to the switch SW4.

(101) The switch SW4 becomes ON state in the case of an inverted bit XD0=1 (high level), and supplies the selection voltage VC supplied from the switch SW3 to the terminal T2 of the amplifier circuit 20 via the terminal Q2 and the filter circuit 43A.

(102) The switch SW5 becomes ON state in the case of an inverted control signal XCTL=1 (high level), and supplies the selection voltage VC received by the terminal TC to the terminal T1 of the amplifier circuit 20 via the terminal Q1 and the filter circuit 43A.

(103) The switch SW6 becomes ON state in the case of the inverted control signal XCTL=1 (high level), and supplies the selection voltage VD received by the terminal TD to the terminal T2 of the amplifier circuit 20 via the terminal Q2 and the filter circuit 43A.

(104) The switch SW7 becomes ON state in the case of the bit D0=1 (high level), and supplies the selection voltage VD received by the terminal TD to the terminal T2 of the amplifier circuit 20 via the terminal Q2 and the filter circuit 43A.

(105) The switch SW8 becomes ON state in the case of the inverted bit XD0=1 (high level), and supplies the selection voltage VC received by the terminal TC to the terminal T1 of the amplifier circuit 20 via the terminal Q1 and the filter circuit 43A.

(106) The switches SW1 to SW8 may be achieved by Pch transistor switches. That is, the conductivity types of the respective transistors are switched, and respective positive signals of the control signal (CTL) and the bit signal (D0) input to the gates of the respective transistors are switched for complementary signals (XCTL, XD0). The circuit configuration of the second sub-decoder 42A that achieves the specifications of FIG. 11A and FIG. 11B is not limited to the circuit configuration illustrated in FIG. 12. For example, the positions of the respective switches that receive the control signals (CTL, XCTL) and the bit signals (D0, XD0) may be changed.

Example 5

(107) FIG. 13A and FIG. 13B are drawings illustrating exemplary operation configurations of the second decoder 40 illustrated in FIG. 9 in the first selection state and the second selection state when the amplifier circuit 20 includes the three terminals T1 to T3 as the input terminals.

(108) Assume that the DA converter circuit illustrated in FIG. 9 outputs the selection voltages in eight stages of the levels 0 to 7 illustrated in FIG. 10B. This range of the selection voltage equivalents to, for example, the voltage range Vdw corresponding to the range A, which has the nonlinear characteristic, of the gamma characteristic curve illustrated in FIG. 2.

(109) The second sub-decoder 42 receives the two different reference voltages VC and VD selected by the first sub-decoder 41, and controls the selection voltages supplied to the terminals T1 to T3 of the amplifier circuit 20 based on the control signal CTL and the bit D0 as the least significant bit in the digital data signal (J1). The weighting ratio of the three terminals T1 to T3 of the amplifier circuit 20 is assumed to be set to 1:1:2.

(110) When being set to the first selection state corresponding to the control signal CTL=0 (low level), the second sub-decoder 42 supplies one selection voltage VC of the selection voltages VC and VD to each of the terminals T1 and T2 of the amplifier circuit 20 as illustrated in FIG. 13A irrespective of the value of the bit D0. Further, the second sub-decoder 42 supplies the other selection voltage VD of the selection voltages VC and VD to the terminal T3 of the amplifier circuit 20 as illustrated in FIG. 13A. At this time, the amplifier circuit 20 receives the selection voltage VC at the terminals T1 and T2, receives the selection voltage VD at the terminal T3, and outputs the voltage (VC+VD)/2 as the weighted average of the selection voltages VC and VD with the weighting ratio of 1:1. Accordingly, in the first selection state, the voltage changes of the terminals T1 to T3 are promptly performed.

(111) When being set to the second selection state corresponding to the control signal CTL=1 (high level), the second sub-decoder 42 supplies the selection voltage VC to each of the terminals T1 to T3 of the amplifier circuit 20 as illustrated in FIG. 13B corresponding to the bit D0=0. The amplifier circuit 20 outputs the voltage VC. Corresponding to the bit D0=1, the second sub-decoder 42 supplies the selection voltage VD to each of the terminals T1 to T3 of the amplifier circuit 20. The amplifier circuit 20 outputs the voltage VD.

(112) As described above, the first-period Tc1 in the first selection state and the second-period Tc2 in the second selection state are provided in the one data period where the voltage output corresponding to the digital data signal (J1) is performed, and in the first-period Tc1, the voltage change of each input terminal of the amplifier circuit 20 is accelerated even when the voltage change is large. That is, in the initial first-period Tc1, processing to increase the change speed of the output voltage of the amplifier circuit 20 is performed to the voltage corresponding to the digital data signal or the voltage at the proximity of the corresponding voltage, and in the subsequent second-period Tc2, driving is stabilized at the voltage corresponding to the digital data signal.

(113) FIG. 14 is a circuit diagram illustrating an exemplary internal configuration of a second sub-decoder 42B configured as the second sub-decoder 42 along the specifications of FIG. 13A and FIG. 13B. The second sub-decoder 42B includes terminals TC and TD that receive mutually different selection voltages VC and VD, Nch transistor switches SW1 to SW8, and terminals Q1 to Q3. A filter circuit 43B is disposed between the terminals Q1 to Q3 and the terminals T1 to T3 of the amplifier circuit 20.

(114) The switch SW1 becomes ON state in the case of the control signal CTL=1 (high level), and supplies the selection voltage VD received by the terminal TD to the switch SW2.

(115) The switch SW2 becomes ON state in the case of the bit D0=1 (high level), and supplies the selection voltage VD supplied from the switch SW1 to the terminals T1 and T2 of the amplifier circuit 20 via the terminals Q1, Q2, and the filter circuit 43B.

(116) The switch SW3 becomes ON state in the case of the control signal CTL=1 (high level), and supplies the selection voltage VC received by the terminal TC to the switch SW4.

(117) The switch SW4 becomes ON state in the case of an inverted bit XD0=1 (high level), and supplies the selection voltage VC supplied from the switch SW3 to the terminal T3 of the amplifier circuit 20 via the terminal Q3 and the filter circuit 43B.

(118) The switch SW5 becomes ON state in the case of an inverted control signal XCTL=1 (high level), and supplies the selection voltage VC received by the terminal TC to the terminals T1 and T2 of the amplifier circuit 20 via the terminals Q1, Q2, and the filter circuit 43B.

(119) The switch SW6 becomes ON state in the case of the inverted control signal XCTL=1 (high level), and supplies the selection voltage VD received by the terminal TD to the terminal T3 of the amplifier circuit 20 via the terminal Q3 and the filter circuit 43B.

(120) The switch SW7 becomes ON state in the case of the bit D0=1 (high level), and supplies the selection voltage VD received by the terminal TD to the terminal T3 of the amplifier circuit 20 via the terminal Q3 and the filter circuit 43B.

(121) The switch SW8 becomes ON state in the case of the inverted bit XD0=1 (high level), and supplies the selection voltage VC received by the terminal TC to the terminals T1 and T2 of the amplifier circuit 20 via the terminals Q1, Q2, and the filter circuit 43B.

(122) The switches SW1 to SW8 illustrated in FIG. 14 may be achieved by Pch transistor switches. That is, the conductivity types of the respective transistors are switched, and respective positive signals of the control signal (CTL) and the bit signal (D0) input to the gates of the respective transistors are switched for complementary signals (XCTL, XD0). The circuit configuration of the second sub-decoder 42B that achieves the specifications of FIG. 13A and FIG. 13B is not limited to the circuit configuration illustrated in FIG. 14. For example, the positions of the respective switches that receive the control signals (CTL, XCTL) and the bit signals (D0, XD0) may be changed.

Example 6

(123) FIG. 15 is a circuit diagram illustrating a configuration of an output unit that outputs the selection voltages of the levels 0 to 7 illustrated in FIG. 10A and FIG. 10B in the first sub-decoder 41.

(124) The first sub-decoder 41 receives eight reference voltages Vr0a, Vr0b, Vr1a, Vr1b, Vr2a, Vr2b, Vr3a, and Vr3b corresponding to the levels 0 to 7, respectively, and a bit D2, an inverted bit XD2, a bit D1, and an inverted bit XD1 as the first sub-bit signal group b1. As illustrated in FIG. 15, the first sub-decoder 41 includes Nch transistor switches SW11 to SW22 and terminals TC and TD as the output ports.

(125) The switch SW11 becomes ON state in the case of the inverted bit XD1=1 (high level), and supplies the reference voltage Vr0a to the switch SW12. The switch SW13 becomes ON state in the case of the bit D1=1 (high level), and supplies the reference voltage Vr1a to the switch SW12. The switch SW12 becomes ON state in the case of the inverted bit XD2=1 (high level), and outputs one of the reference voltage Vr0a supplied from the switch SW11 and the reference voltage Vr1a supplied from the switch SW13 as the selection voltage VC via the terminal TC.

(126) The switch SW14 becomes ON state in the case of the inverted bit XD1=1 (high level), and supplies the reference voltage Vr2a to the switch SW15. The switch SW16 becomes ON state in the case of the bit D1=1 (high level), and supplies the reference voltage Vr3a to the switch SW15. The switch SW15 becomes ON state in the case of the bit D2=1 (high level), and outputs one of the reference voltage Vr2a supplied from the switch SW14 and the reference voltage Vr3a supplied from the switch SW16 as the selection voltage VC via the terminal TC.

(127) The switch SW17 becomes ON state in the case of the inverted bit XD1=1 (high level), and supplies the reference voltage Vr0b to the switch SW18. The switch SW19 becomes ON state in the case of the bit D1=1 (high level), and supplies the reference voltage Vr1b to the switch SW18. The switch SW18 becomes ON state in the case of the inverted bit XD2=1 (high level), and outputs one of the reference voltage Vr0b supplied from the switch SW17 and the reference voltage Vr1b supplied from the switch SW19 as the selection voltage VD via the terminal TD.

(128) The switch SW20 becomes ON state in the case of the inverted bit XD1=1 (high level), and supplies the reference voltage Vr2b to the switch SW21. The switch SW22 becomes ON state in the case of the bit D1=1 (high level), and supplies the reference voltage Vr3b to the switch SW21. The switch SW21 becomes ON state in the case of the bit D2=1 (high level), and outputs one of the reference voltage Vr2b supplied from the switch SW20 and the reference voltage Vr3b supplied from the switch SW22 as the selection voltage VD via the terminal TD.

(129) With this configuration, the first sub-decoder 41 selects one of the reference voltages Vr0a, Vr1a, Vr2a, and Vr3a corresponding to the even number gradations as the selection voltage VC corresponding to the first sub-bit signal group b1 (D2, XD2, D1, XD1). Further, the first sub-decoder 41 selects one of the reference voltages Vr0b, Vr1b, Vr2b, and Vr3b corresponding to the odd number gradations as the selection voltage VD. For the selection voltages VC and VD, the reference voltages adjacent to one another having a small electric potential difference between both reference voltages are preferred to be selected. Accordingly, the change amount of the output voltage of the amplifier circuit 20 can be decreased at the time of switch from the first-period Tc1 to the second-period Tc2 in the one data period to ensure a smooth waveform of the output voltage.

(130) While the circuit of the first sub-decoder 41 illustrated in FIG. 15 includes a minimum number of transistor switches, a configuration where the order of selection based on the bits D1 and D2 is switched may be employed. Furthermore, the size of the range A of FIG. 10A and FIG. 10B is also changeable as necessary.

Example 7

(131) FIG. 16A and FIG. 16B are circuit diagrams illustrating specific examples of the filter circuit 43 described above.

(132) FIG. 16A is a diagram illustrating a circuit of the filter circuit 43A when the number N of the input terminals of the amplifier circuit 20 is N=2, and FIG. 16B is a diagram illustrating a circuit of the filter circuit 43B when the number N of the input terminals of the amplifier circuit 20 is N=3.

(133) The filter circuit 43A or 43B is disposed to avoid occurrence of unexpected short circuit between the outputs of the first decoder 30 and the second decoder 40, and disposed to any one of the first decoder 30 and the second decoder 40. In this example, the operation is described with a configuration where the filter circuit 43A or 43B is disposed to the second decoder 40.

(134) The filter circuit 43A illustrated in FIG. 16A is disposed between the terminals Q1 and Q2 as the output ports of the second sub-decoder 42A and the terminals T1 and T2 of the amplifier circuit 20 illustrated in FIG. 12.

(135) The circuit illustrated in FIG. 16A includes Nch transistor switches SW31 and SW32.

(136) The switch SW31 becomes ON state in the case of an inverted bit XD3=1 (high level), where the inverted bit XD3 is obtained by inverting a logic level of the bit D3 as the third sub-bit signal group b3, and the switch SW31 electrically connects the terminal Q1 of the second sub-decoder 42A to the terminal T1 of the amplifier circuit 20. In the case of the inverted bit XD3=0 (low level), the switch SW31 becomes OFF state, and cuts off the electrical connection between the terminal Q1 and the terminal T1.

(137) The switch SW32 becomes ON state in the case of the inverted bit XD3=1 (high level), and electrically connects the terminal Q2 of the second sub-decoder 42A to the terminal T2 of the amplifier circuit 20. Meanwhile, in the case of the inverted bit XD3=0 (low level), the switch SW32 becomes OFF state, and cuts off the electrical connection between the terminal Q2 and the terminal T2.

(138) With this configuration, the filter circuit 43A illustrated in FIG. 16A establishes a conduction between the output ports (Q1, Q2) of the second sub-decoder 42A and the input terminals (T1, T2) of the amplifier circuit 20 only when the level of the digital data signal is in the range A indicated in the specification of FIG. 10A, and cuts off the conduction when the level of the digital data signal is out of the range A.

(139) Instead of the filter circuit 43A, another filter circuit that connects the second sub-decoder 42A to the amplifier circuit 20 only when the bit value is in the range B may be disposed between the output of the first decoder 30 and the input terminal of the amplifier circuit 20.

(140) The filter circuit 43B illustrated in FIG. 16B is disposed between the terminals Q1 to Q3 as the output ports of the second sub-decoder 42B illustrated in FIG. 14 and the terminals T1 to T3 of the amplifier circuit 20.

(141) The circuit illustrated in FIG. 16B includes Nch transistor switches SW41 to SW43, and SW51 to 53.

(142) The switches SW41 to SW43 become ON state in the case of an inverted bit XD3=1 (high level), where the inverted bit XD3 is obtained by inverting a logic level of the bit D3 as the third sub-bit signal group b3, and become OFF state in the case of the inverted bit XD3=0 (low level). The switches SW51 to SW53 become ON state in the case of an inverted bit XD4=1 (high level), where the inverted bit XD4 is obtained by inverting a logic level of the bit D4 as the third sub-bit signal group b3, and become OFF state in the case of the inverted bit XD4=0 (low level).

(143) When both the switches SW41 and SW51 become ON state, the terminal Q1 of the second sub-decoder 42B is electrically connected to the terminal T1 of the amplifier circuit 20, and when any one of them becomes OFF state, the connection between the terminal Q1 and the terminal T1 is cut off. When both the switches SW42 and SW52 become ON state, the terminal Q2 of the second sub-decoder 42B is electrically connected to the terminal T2 of the amplifier circuit 20, and when any one of them becomes OFF state, the connection between the terminal Q2 and the terminal T2 is cut off. Furthermore, when both the switches SW43 and SW53 become ON state, the terminal Q3 of the second sub-decoder 42B is electrically connected to the terminal T3 of the amplifier circuit 20, and when any one of them becomes OFF state, the connection between the terminal Q3 and the terminal T3 is cut off.

(144) With this configuration, the filter circuit 43B illustrated in FIG. 16B establishes a conduction between the output ports (Q1 to Q3) of the second sub-decoder 42B and the input terminals (T1 to T3) of the amplifier circuit 20 only when the level of the digital data signal is in the range A indicated in the specification of FIG. 10B, and cuts off the conduction when the level of the digital data signal is out of the range A.

(145) It is understood that the foregoing description and accompanying drawings set forth the preferred embodiments of the present invention at the present time. Various modifications, additions and alternative designs will, of course, become apparent to those skilled in the art in light of the foregoing teachings without departing from the spirit and scope of the disclosed invention. Thus, it should be appreciated that the present invention is not limited to the disclosed Examples but may be practiced within the full scope of the appended claims. This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2019-45062 filed on Mar. 12, 2019, the entire contents of which are incorporated herein by reference.