DC input current ripple reduction in SRM drive for high volumetric power density applications

Abstract

A control system for a switched reluctance machine includes a capacitor and an inverter connected to the capacitor, wherein the inverter generates current signals and a ripple current returned to the capacitor. A switched reluctance machine (SRM) receives the current signals and generates a position signal. A controller receives the ripple current, current signal values of the current signals, and the position signal and generates desired reference current waveforms received by the inverter to adjust the current signals received by the SRM.

Claims

1. A control system for a switched reluctance machine, comprising: a capacitor; an inverter connected to said capacitor and generating current signals and a ripple current returned to said capacitor; a switched reluctance machine (SRM) receiving said current signals and generating a position signal; and a controller receiving said ripple current, current signal values of said current signals, and said position signal, and generating desired reference current waveforms received by said inverter to adjust said current signals received by said SRM.

2. The system according to claim 1, comprising: a high pass filter connected to said capacitor, said capacitor receiving said ripple current and filtering low frequency currents and sending high frequency components to said controller.

3. The system according to claim 2, wherein said high pass filter passes high frequency components to about 32 Hz and above.

4. The system according to claim 2, wherein said ripple current is compared to a desired ripple current value for use in generating said desired reference current waveforms.

5. The system according to claim 4, wherein said position signal is converted to an actual speed signal and is compared to a reference speed signal for use in generating said desired reference current waveforms.

6. The system according to claim 5, further comprising: a first proportional integral controller for receiving a difference between said actual speed signal and said reference speed signal so as to generate a reference current signal; a second proportional integral controller for receiving a difference between said ripple current and said desired ripple current so as to generate an adjustment signal; and an adjustment circuit to receive said reference current signal and said adjustment signal to generate said desired reference current waveforms.

7. The system according to claim 6, wherein said adjustment circuit uses the following equation
i.sub.ref(θ,ω.sub.ref)=[I.sub.PI1(ω.sub.actual,θ)−I.sub.PI2(I.sub.DC ripple)] wherein I.sub.PI1 is said adjustment signal and I.sub.PI2 is said reference current signal.

8. A method for reducing DC input current ripple, comprising: connecting an inverter to a capacitor and generating current signals; receiving said current signals in a switched reluctance machine (SRM) which generates a ripple current received by said capacitor and a position signal; receiving said ripple current, current signal values of said current signals and said position signal in a controller which generates desired reference current waveforms; and receiving said desired reference current waveforms in said inverter to adjust said current signals in said SRM and reduce said ripple current.

9. The method according to claim 8, further comprising: receiving said ripple current in a high pass filter from said capacitor and sending selected high frequency components of said ripple current to said controller.

10. The method according to claim 9, further comprising: comparing said ripple current to a desired ripple current value for use in generating said desired reference current waveforms.

11. The method according to claim 10, further comprising: converting said position signal to an actual speed signal; and comparing said actual speed signal to a reference speed signal for use in generating said desired reference current waveforms.

12. The method according to claim 11, further comprising: receiving a difference between said actual speed signal and said reference speed signal in a first proportional integral controller which generates a reference current signal; receiving a difference between said ripple current and said desired ripple current in a second proportional integral controller which generates an adjustment signal; and receiving said reference current signal and said adjustment signal in an adjustment circuit to generate said desired reference current waveforms.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) For a complete understanding of the objects, techniques and structure of the invention, reference should be made to the following detailed description and accompanying drawings, wherein:

(2) FIG. 1 is a schematic diagram of a switched reluctance machine (SRM) and associated control system according to the concepts of the present invention;

(3) FIG. 2 is a schematic diagram of a current ripple reduction circuit incorporated into the control system for the SRM according to the concepts of the present invention;

(4) FIGS. 3A-D are graphical representations of torque profile, phase current, input DC current and a fast Fourier transform of a SRM without a speed control;

(5) FIGS. 4A-D are graphical representations of torque profile, phase current, input DC current and a fast Fourier transform of a SRM obtained from a current ripple reduction circuit according to the concepts of the present invention; and

(6) FIG. 5 is a graphical representation showing a battery input current comparing a 18 mF capacitor yield with the same ripple current as a 2 mF would with the inventive current ripple reduction circuit according to the concepts of the present invention.

BEST MODE FOR CARRYING OUT THE INVENTION

(7) In general, a DC link current ripple reduction in a switched reluctance machine (SRM) drive by current profiling is disclosed. A main objective of a control system and associated algorithm is to inject an appropriate amount of the current ripple obtained from a DC link current to a reference current of the SRM in order to generate optimal current profiles while maintaining the machine performance unchanged. As alluded to above, the ripple current is generated by the inverter due to the non-linear behavior of the SRM. The inverter is generating phase currents received by the SRM. Output power from the inverter to the SRM is very close to the input power to the inverter from the battery. Since the SRM has non-linear behavior, the power taken by the SRM has a ripple, which impacts the power taken by the inverter from the battery. As a result, a steady DC bus voltage ripple on the input power to the inverter means a ripple on the DC bus current.

(8) Referring now to the drawings, and in particular to FIG. 1, it can be seen that a control system which may incorporate an associated algorithm is designated generally by the numeral 10. As can be seen, the system 10 includes a switched reluctance machine (SRM) 12, which may be of any various sizes. As will be understood by those skilled in the art, the SRM 12 provides for observable characteristics such as torque, speed, and power control, to name a few. A battery 14 powers the SRM 12, wherein a DC link capacitor 16 is connected in parallel to the battery. Connected in parallel to the capacitor 16 may be an inverter 18. Although various types of inverters may be employed, the present embodiment employs an asymmetric half bridge which comprises insulated gate bipolar transistors (IGBT) S1-S6 and associated diodes wherein the inverter 18 is employed to invert the DC power transferred by the capacitor into a three-phase signal (I.sub.a, I.sub.b, I.sub.c) received by the SRM 12. The inverter generates phase currents 20 (shown as A+, A−, B+, B−, C+, and C− in FIG. 1) which are monitored by a corresponding current sensor 22 so as to determine the values of current phases I.sub.a, I.sub.b, and I.sub.c. The current sensors 22 generate a sensed current signal 24. In any event, the phase currents 20 are delivered to the SRM 12 which in turn powers or drives a load 28.

(9) Associated with the SRM 12 and the inverter 18, which are a part of the control system 10, may be a speed controller 34. Skilled artisans will appreciate that the speed controller 34 monitors the operation of the SRM and other components of the system 10 and assists in providing input to the inverter 18 so as to adjust the currents received by the SRM 12.

(10) Associated with the SRM 12 may be a resolver 36. In particular, the resolver 36 is coupled to a rotor of the SRM 12 and an associated decoder to determine a rotor position of the SRM 12 wherein this information is input to the speed controller 34. The resolver generates a position signal 38 which is received by a commutation angle and hysteresis control 42 which also receives the sensed current 24 from the current sensors 22. The position signal 38 may also be delivered to an integrator, shown as d/dt in FIG. 1, so as to generate a speed .sub.actual value 46.

(11) A summation circuit 50 may receive a negative value of the speed .sub.actual value 46 along with a speed .sub.ref value 52. The speed .sub.ref value 52 may be input by a user to obtain a desired operation of the SRM. In other embodiments the value 52 may be automatically adjusted based on predetermined or observed operating characteristics of the system 10. In any event, the summation circuit 50 may generate a speed adjustment value 53 that is delivered to a speed control circuit 54. The speed control circuit delivers a control signal 56 to the commutation angle and hysteresis control 42 which together with the observed position signal 38 and the sensed current signal 24 generates adjustment signals 58 which are delivered to gate drives 60. It will be appreciated that there may be a gate drive 60 associated with each corresponding IGBT S1-S6 incorporated into the inverter 18. Accordingly, the gate drives generate gate signals G1-G6 62 which are received by a corresponding transistor S1-S6 in the inverter.

(12) In summary, the control system 10 provides for an asymmetric half bridge inverter 18 to generate supply phase currents for use as individual phases by the SRM 12. Although there are many strategies to control the operation of SRM 12 such as torque, speed, or power control, the present embodiment employs the speed controller as an outer loop to determine the level of the phase currents. The speed controller 34 defines a reference current to maintain a desired speed level. As noted, the resolver 36, which is connected to the shaft of the SRM 12, detects the position of the SRM's rotor and a decoder is used to obtain the rotor position. The commutation angle and hysteresis control 42 receives the reference sensed current signal 24 and defines the current commutation time interval for each phase based on the turn-on (T.sub.on) and turn-off (T.sub.off) angles associated with the commutator of the SRM 12. Within the commutation angle and hysteresis control 42 may be a hysteresis current block which controls the current in a desired range and manages the timing gate signals 62 of the transistors maintained in the inverter block. Next, the inverter 18 manages phase voltages to supply the desired current to each phase. Phase current sensors 22 may feed the commutation angle and hysteresis current control to supply accurate current values to each phase winding.

(13) In the present embodiment, SRM speed and DC link current ripple may be utilized as system feedbacks which may be controlled so as to reduce the DC link current while keeping the SRM 12 at the desired speed.

(14) Referring now to FIG. 2, it can be seen that a current ripple reduction circuit is designated generally by the numeral 70 and which may be directly incorporated into the controller 34 or may be otherwise connected to the controller 34. The circuit 70 monitors the DC link capacitor 16 for the purposes of reducing the ripple current generated thereby. The capacitor 16 may be connected to a high pass filter (HPF) 72 which generates a current ripple signal 74. As will be understood by skilled artisans, the filter 72 may be configured to remove unwanted or undesired low frequency components detrimental to operation of the system 10. The current ripple signal 74 is delivered to a speed and ripple controller designated generally by the numeral 76 which receives the current ripple signal 74 along with the speed .sub.actual value 46.

(15) The controller 76 employs a proportional integral controller in the speed control 54 which receives the summation signal 53 generated by the summation circuit 50. The controller 54 accordingly generates the I.sub.ref signal 56. In a somewhat similar manner, a summation circuit 86 receives a ripple .sub.Desired value 88, which may be input by a user or otherwise set, and a negative value of the current ripple signal 74. The circuit 86 generates a signal which is received by a proportional integral controller in a ripple control 90 so as to generate an adjustment signal 92.

(16) An adjustment circuit 96 receives both a negative value of the adjustment signal 92 and the I.sub.ref signal 56 so as to generate desired reference current waveforms 98 which are received by the commutation angle and hysteresis control 42. The control 42 may then generate and deliver the adjustment signals 58 to the gate drives 60, as shown in FIG. 1, for delivery of the gate signals 62 to the corresponding transistors S1-S6 for use by the inverter 18.

(17) In summary, the outer speed controller 34, with the incorporated current ripple reduction circuit 70, operates at a lower bandwidth and generates a desired average value for the phase currents. In order to acquire DC link current ripple, the high pass filter 72 is implemented. The DC link current ripple is processed through the controller 76 to generate a profile to be added to the average reference current waveform. The output of the controls 54 and 90 are coordinated through the control algorithm in circuit 96 to generate the desired reference current waveforms 98 using Equation 1:
i.sub.ref(θ,ω.sub.ref)=[I.sub.PI1(ω.sub.actual,θ)−I.sub.PI2(I.sub.DC ripple)]  (1)

(18) Where, I.sub.PI1 and I.sub.PI2 are the output of the controls 54 and 90 from the speed and DC link current ripple block respectively. DC ripple refers to the current ripple signal 74. Furthermore, θ represents the rotor position of the SRM 12, ω.sub.ref represents the desired rotor speed and ω.sub.actual is the actual rotor speed.

(19) Equation 2 describes the transfer function of the high pass filter (HPF) 72. The cut-off frequency of the HPF in the present embodiment is chosen 32 Hz such that it filters the DC and low frequency components around the DC and sends the high frequency components to the controller.

(20) $\begin{array}{cc}H\left(s\right)=\frac{\mathrm{Ts}}{1+\mathrm{Ts}}& \left(2\right)\end{array}$

(21) Wherein T is the coefficient of the high pass filter 72, and s is a complex mathematical complex frequency domain for the Laplace transformation.

(22) The system 10 and the reduction circuit 70 of the present embodiment are designed for an automotive application where space is limited and where the power density requirement is high. Skilled artisans will appreciate that the system 10 and the reduction circuit 70 may be used in many other applications. The parameters of the system 10 and the reduction circuit 70 are shown in Table I. For the specified size, a 2 mF DC link capacitor is used at most. Unfortunately, the input ripple, without a ripple reduction control, is found as 275% by using this value, which is very high.

(23) TABLE-US-00001 TABLE 1 Parameter Value Average Torque 360 Nm Speed 500 rpm Reference Current 350 A Input Battery Voltage 350 V DC Link Capacitor 2 mF

(24) FIGS. 3A-D show the torque profile, phase currents, input DC current and its Fourier components without a speed control. The allowable ripple is set to be around 50%. FIGS. 4A-D show the results after implementing the control scheme with the current ripple reduction circuit where the input current ripple decreases to 47.97%. It is also evident in comparing the Fourier analysis in FIGS. 3D and 4D, where the major ripple components are decreased to a lower value than the ripple of the DC input current obtained in the conventional scheme. The comparison of torque, voltage and current ripple is shown in Table II below. From FIGS. 3A and 4A, it can be seen that the torque profile is almost unchanged as well as the efficiency of the SRM.

(25) TABLE-US-00002 TABLE II Without With ripple control control Input Voltage Ripple (%) 6.07 1.73 Input Current Ripple (%) 275.86 47.97 Torque ripple (%) 27.78 27.02 Torque per phase RMS current (Nm/A) 1.446 1.478

(26) In order to observe the effect of this technique on the size of the overall system and thus on the volumetric power density, the simulation is performed to achieve the required ripple by increasing the value of capacitance without the control scheme. It is found that an 18 mF capacitor yields same ripple current as the 2 mF capacitor would with the proposed control. FIG. 5 shows the battery input current in both cases with same peak-to-peak ripple. So, utilizing the control disclosed herein, a smaller capacitor is required which leads to an increase in the volumetric power density.

(27) The disclosed system 10 has many advantages. First, reduction of DC link current ripple in the SRM drive is performed to achieve high volumetric power density and compact size requirement. The allowable ripple is achieved without modifying the performance of the SRM machine. This facilitates SRM use in automotive and other applications.

(28) Thus, it can be seen that the objects of the invention have been satisfied by the structure and its method for use presented above. While in accordance with the Patent Statutes, only the best mode and preferred embodiment has been presented and described in detail, it is to be understood that the invention is not limited thereto or thereby. Accordingly, for an appreciation of the true scope and breadth of the invention, reference should be made to the following claims.