Semiconductor device and method for manufacturing same

Abstract

A multi-finger transistor including plural control electrodes (2), plural first electrodes (3), and plural second electrodes (4) is provided on a semiconductor substrate (1). A resin film (14,15) covers the transistor. A first wiring (8) electrically connecting the plural first electrodes (3) to one other is provided on the resin film (14,15). The resin film (14,15) covers contact portions between the first wiring (8) and the plural first electrodes (3). A first hollow structure (16) sealed with the resin film (14,15) is provided around the plural control electrodes (2) and the plural second electrodes (4).

Claims

1. A semiconductor device comprising: a semiconductor substrate; a multi-finger transistor including plural control electrodes, plural first electrodes, and plural second electrodes provided on the semiconductor substrate; a first resin film formed on the semiconductor substrate; a second resin film covering the multi-finger transistor and contacting the first resin film; and a first wiring provided on the second resin film and electrically connecting the plural first electrodes to one other, wherein the first resin film covers part of contact portions between the first wiring and the plural first electrodes which is formed on a region of the multi-finger transistor, and a first hollow structure sealed with the second resin film is provided around the plural control electrodes and one of the plural second electrodes, wherein the second resin film defines an upper surface of the first hollow structure.

2. The semiconductor device according to claim 1, further comprising a second wiring provided on the semiconductor substrate, covered with the second resin film, and electrically connecting the plural control electrodes to one other, wherein a second hollow structure sealed with the second resin film is provided at an intersection portion of the first wiring and the second wiring.

3. The semiconductor device according to claim 1, wherein the first wiring is provided above the plural control electrodes and the plural second electrodes.

4. The semiconductor device according to claim 3, further comprising a lower layer wiring covered with the second resin film, and an upper layer wiring provided on the second resin film, wherein a second hollow structure sealed with the second resin film is provided at an intersection portion of the lower layer wiring and the upper layer wiring.

5. The semiconductor device according to claim 4, further comprising a support pole supporting the second resin film and provided inside the second hollow structure.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) FIG. 1 is a plan view showing a semiconductor device according to a first embodiment of the present invention.

(2) FIG. 2 is a cross-sectional view taken along I-IT of FIG. 1.

(3) FIG. 3 is a cross-sectional view taken along III-IV of FIG. 1.

(4) FIG. 4 is a cross-sectional view showing the method of manufacturing a semiconductor device according to the first embodiment of the present invention.

(5) FIG. 5 is a cross-sectional view showing the method of manufacturing a semiconductor device according to the first embodiment of the present invention.

(6) FIG. 6 is a cross-sectional view showing the method of manufacturing a semiconductor device according to the first embodiment of the present invention.

(7) FIG. 7 is a cross-sectional view showing the method of manufacturing a semiconductor device according to the first embodiment of the present invention.

(8) FIG. 8 is a cross-sectional view showing the method of manufacturing a semiconductor device according to the first embodiment of the present invention.

(9) FIG. 9 is a plan view showing a semiconductor device according to a second embodiment of the present invention.

(10) FIG. 10 is a cross-sectional view taken along I-II of FIG. 9.

(11) FIG. 11 is a cross-sectional view showing a semiconductor device according to a third embodiment of the present invention.

(12) FIG. 12 is a cross-sectional view showing a semiconductor device according to a fourth embodiment of the present invention.

(13) FIG. 13 is a plan view showing a semiconductor device according to a fifth embodiment of the present invention.

(14) FIG. 14 is a cross-sectional view taken along I-II of FIG. 13.

DESCRIPTION OF EMBODIMENTS

(15) A semiconductor device and a method for manufacturing same according to the embodiments of the present invention will be described with reference to the drawings. The same components will be denoted by the same symbols, and the repeated description thereof may be omitted.

First Embodiment

(16) FIG. 1 is a plan view showing a semiconductor device according to a first embodiment of the present invention. FIG. 2 is a cross-sectional view taken along I-II of FIG. 1. FIG. 3 is a cross-sectional view taken along III-IV of FIG. 1. A multi-finger field effect transistor including plural gate electrodes 2, plural source electrodes 3, and plural drain electrodes 4 is formed on a semiconductor substrate 1. The cross-sectional shape of the gate electrode 2 is T-type or Y-type. The plural gate electrodes 2 are connected to a gate pad 6 via a gate wiring 5. The plural source electrodes 3 are connected to a source pad 9 via a source wiring 7 and a connection wiring 8. The plural drain electrodes 4 are connected to a drain pad 11 via a drain wiring 10.

(17) Insulating films 12 and 13 and resin films 14 and 15 cover the transistor. The connection wiring 8 is formed on the resin film 15. The connection wiring 8 and the source wiring 7 electrically connect the plural source electrodes 3 to one other. The resin film 14 covers contact portions between the connection wiring 8 and the plural source electrodes 3. Hollow structures 16 sealed with the resin films 14 and 15 are formed around the plural gate electrodes 2 and the plural drain electrodes 4. Furthermore, a hollow structure 17 sealed with the resin films 14 and 15 is formed at an intersection portion of the gate wiring 5 and the connection wiring 8.

(18) The thicknesses of the resin films 14 and 15 are equal to 2 to 20 μm. The heights of the hollow structures 16 and 17 are equal to 1 to 10 μm. The widths and depths of the hollow structures 16 and 17 are equal to several μm to several hundreds μm. The hollow structures 16 and 17 are formed not over the whole chip, but for each of elements of a circuit such as a transistor and a wiring.

(19) Subsequently, a method of manufacturing a semiconductor device according to the present embodiment will be described. FIGS. 4 to 8 are cross-sectional views showing the method of manufacturing a semiconductor device according to the first embodiment of the present invention. FIGS. 4, 6 and 8 correspond to the cross-sectional view of FIG. 2, and FIGS. 5 and 7 correspond to the cross-sectional view of FIG. 3.

(20) First, as shown in FIGS. 4 and 5, a transistor having the gate electrodes 2, the source electrodes 3, and the drain electrodes 4 is formed on the semiconductor substrate 1. At this time, lower layer wirings such as the gate wiring 5 are simultaneously formed. The insulating film 12 is formed on the entire surface. The insulating film 12 is opened at a place to which an electrical wiring is connected in a subsequent step. Next, the resin film 14 which is a photosensitive resin film is formed on the entire surface by a coating method using a spin coater, or a laminating method, or an STP (Spin-coating film Transfer and hot-Pressing technology) method. The resin film 14 is subjected to patterning by exposure and development so that the source electrodes 3 are covered while the gate electrodes 2 and the drain electrodes 4 are not covered, but surrounded. By using the photosensitive resin film as described above, the resin film 14 can be easily patterned. Furthermore, the resin film 14 is also opened in a region on the gate wiring 5 which will become the intersection portion of the wirings later. Thereafter, curing processing is performed to cure the resin film 14.

(21) Next, as shown in FIGS. 6 and 7, a sheet film of a photosensitive resin film as the resin film 15 is bonded to the upper surface of the resin film 14 by the laminating method or the STP method. As a result, the hollow structure 16 sealed with the resin films 14 and 15 is formed around the gate electrodes 2 and the drain electrode 4. At the same time, the hollow structure 17 can be formed in a region above the gate wiring 5 on the same plane.

(22) Next, as shown in FIG. 8, the resin film 15 is exposed and developed to form through holes 18 above the source electrodes 3 and the like. Thereafter, the curing processing is performed to cure the resin film 15. The resin film 15 may be non-photosensitive resin, and in this case, dry etching is used when the through holes 18 are formed.

(23) Next, the connection wiring 8 connected to the source electrodes 3 through the through holes 18 is formed on the resin film 15 by plating or vapor deposition. In the case of the plating, a power supply layer is formed, patterning is performed with a resist, and then electrolytic plating is performed. Thereafter, the resist and the power supply layer are removed. On the other hand, in the case of the vapor deposition method, patterning is performed with a resist, a metal film is formed by vapor deposition, and the resist is removed by a lift-off method. Finally, the outside of the resin film 14 and the outside of the resin film 15 are covered with the insulating film 13. However, portions required for contacts are opened. As a result, the semiconductor device according to the present embodiment is manufactured.

(24) In the present embodiment, the hollow structures 16 sealed with the resin films 14 and 15 are formed around the gate electrodes 2 and the drain electrodes 4. By expanding the hollow structures of the transistor as described above, the capacitance of the transistor can be reduced as much as possible as compared with a case where the hollow structures are formed only around the gate electrodes 2. As a result, the capacitance can be reduced to enhance the high frequency characteristics.

(25) The resin film 14 covers the contact portion between the connection wiring 8 and the source electrode 3. As a result, when the resin film 15 is pasted as shown in FIG. 6, the hollow structures 16 are completely sealed. Therefore, resists or chemicals such as an inorganic aqueous solution which are used in steps after formation of the hollow structures 16 can be prevented from entering the hollow structures 16.

(26) Furthermore, the hollow structure 17 sealed with the resin films 14 and 15 is formed at the intersection portion of the gate wiring 5 and the connection wiring 8. By forming the hollow structure between the wirings as described above, the wiring capacitance can be reduced, so that characteristic impedance can be increased. Therefore, impedance matching can be easily achieved, and circuit design can be facilitated. Note that the hollow structure 17 may be formed at an intersection portion of the gate wiring 5 and the drain wiring 10.

Second Embodiment

(27) FIG. 9 is a plan view showing a semiconductor device according to a second embodiment of the present invention. FIG. 10 is a cross-sectional view taken along I-II of FIG. 9. The connection wiring 8 is formed above the plural gate electrodes 2 and the plural drain electrodes 4 and on the resin film 15, and electrically connects the plural source electrodes 3 to another. The connection wiring 8 extends in a direction perpendicular to the longitudinal direction of the drain electrodes 4. The other configuration is the same as that of the first embodiment, and even in this case, the same effect as the first embodiment can be obtained.

Third Embodiment

(28) FIG. 11 is a cross-sectional view showing a semiconductor device according to a third embodiment of the present invention. A lower layer wiring 19 and an upper layer wiring 20 are formed in a region other than a field effect transistor. The lower layer wiring 19 is covered with the resin films 14 and 15, and the upper layer wiring 20 is formed on the resin film 15. The hollow structure 17 sealed with the resin films 14 and 15 is formed at an intersection portion of the lower layer wiring 19 and the upper layer wiring 20. By forming the hollow structure between the wirings as described above, the wiring capacitance can be reduced, so that characteristic impedance can be increased. Therefore, impedance matching can be easily achieved, and circuit design can be facilitated. The other configuration and effect are the same as the second embodiment.

Fourth Embodiment

(29) FIG. 12 is a cross-sectional view showing a semiconductor device according to a fourth embodiment of the present invention. Support poles 21 for supporting the resin film 15 above the hollow structures 16 and 17 are formed inside the hollow structures 16 and 17. As a result, it is possible to prevent the resin film 15 from hanging down and prevent defects in the process. Although the capacitance of the device is increased as compared with the third embodiment, the structure can be stably formed, so that production stability is enhanced. The other configuration and effect are the same as the third embodiment.

Fifth Embodiment

(30) FIG. 13 is a plan view showing a semiconductor device according to a fifth embodiment of the present invention. FIG. 14 is a cross-sectional view taken along I-II of FIG. 13. A multi-finger bipolar transistor including plural base electrodes 22, plural emitter electrodes 23, and plural collector electrodes 24 is formed on a semiconductor substrate 1. The plural base electrodes 22 are connected to a base pad 26 via a base wiring 25. The plural emitter electrodes 23 are connected to an emitter pad 28 via a connection wiring 27. The plural collector electrodes 24 are connected to a collector pad 30 via a collector wiring 29.

(31) The connection wiring 27 for electrically connecting the plural emitter electrodes 23 to each other is formed on the resin film 15. The resin film 14 covers contact portions between the connection wiring 27 and the plural emitter electrodes 23. The hollow structures 16 sealed with the resin films 14 and 15 are formed around the plural base electrodes 22 and the plural collector electrodes 24. Even in the case of such a bipolar transistor, the same effect as the first and second embodiments can be obtained.

(32) Furthermore, as in the third embodiment, the second hollow structure may be formed at the intersection portion of the wirings. As a result, since the wiring capacitance is reduced, the characteristic impedance can be increased. Therefore, impedance matching can be easily achieved, and circuit design can be facilitated.

REFERENCE SIGNS LIST

(33) 1 semiconductor substrate; 2 gate electrode (control electrode); 3 source electrode (first electrode); 4 drain electrode (second electrode); 5 gate wiring (second wiring); 8,27 connection wiring (first wiring); 14,15 resin film; 16,17 hollow structure; 19 lower layer wiring; 20 upper layer wiring; 21 support pole; 22 base electrode (control electrode); 23 emitter electrode (first electrode); 24 collector electrode (second electrode)