Controller

Abstract

Provided is a controller in which resources can be safely shared by a plurality of processors, such as multi-processors or multi-core processors. The controller is provided with the plurality of processors which each manage the resources or share the resources and include a first processor configured to perform processing with an influence on the integrity of the resources and a second processor. The second processor performs sequence processing for maintaining the integrity of the resources in accordance with the contents of the processing by the first processor, upon receiving a request message requesting the processing to be started.

Claims

1. A controller comprising a plurality of processors which each manage resources or share resources, the controller comprising: a first processor configured to control a machine; and a second processor configured to control the machine, wherein the controller is configured to: control, by the first processor and the second processor, the machine, transmit, by the second processor, a request message for backup processing to the first processor, the message identifying data sets to be backed up, and enter by the second processor, a second standby state after the transmission of the request message, when the request message is received, complete processing, by the first processor, the identified data sets for controlling the machine, when the processing of the identified data sets is complete, transmit, by the first processor, a ready message to the second processor, and enter by the first processor, a first standby state after the transmission of the ready message, when the ready message is received, perform, by the second processor the backup processing of the identified data sets, when the backup processing is complete, transmit, by the second processor, an end message to the first processor, and when the end message is received, resume, by the first processor, controlling the machine.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) The above and other objects and features of the present invention will be obvious from the following description of embodiments with reference to the accompanying drawings, in which:

(2) FIG. 1 is a diagram showing an example of occurrence of data inconsistency;

(3) FIG. 2 is a diagram showing an example of occurrence of data inconsistency;

(4) FIG. 3 is a diagram showing an example of occurrence of data inconsistency;

(5) FIG. 4 is a diagram showing the function and operation of a controller;

(6) FIG. 5 is a diagram showing the function and operation of the controller;

(7) FIG. 6 is a diagram showing the operation of the controller;

(8) FIG. 7 is a diagram showing the function and operation of the controller;

(9) FIG. 8 is a diagram showing the operation of the controller;

(10) FIG. 9 is a diagram showing a hardware configuration of the controller; and

(11) FIG. 10 is a diagram showing the relationship between processors.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

Embodiment 1

(12) FIG. 9 is a schematic hardware configuration diagram showing a controller 1 according to Embodiment 1 of the present invention. The controller 1 is a numerical controller that, for example, reads a program and controls a machine such as a machine tool, robot, or the like. The controller 1 comprises a plurality of processors 11 (two of the processors (11a and 11b) are illustrated in FIG. 9 as an example), ROM (read-only memory) 12, RAM (random access memory) 13, non-volatile memory 14, interface 18, bus 10, axis control circuit 16, and servo amplifier 17. The interface 18 is connected with, for example, a control panel 60.

(13) The processors 11 are processors for generally controlling the controller 1. The processors 11 read out system programs stored in the ROM 12 via the bus 10 and control the entire controller 1 according to the system programs.

(14) In the present embodiment, the controller 1 comprises the plurality of processors 11 (11a and 11b). Each of the processors 11 (11a and 11b) is equivalent to each core of each processor or multi-core processor in a multi-processor environment, for example.

(15) The ROM 12 previously stores system programs for executing various controls of the machine.

(16) The RAM 13 temporarily stores temporary calculation data and display data, data and the like input by an operator through the control panel 60. The RAM 13 is, for example, a DRAM (dynamic random access memory).

(17) The non-volatile memory 14 is backed up by, for example, a battery (not shown). Therefore, the non-volatile memory 14 maintains its storage state even when the controller 1 is shut down. The non-volatile memory 14 is, for example, a battery-backed SRAM (static random access memory). The non-volatile memory 14 is used as, for example, a backup storage for data on the RAM 13.

(18) The axis control circuit 16 controls the motion axes of the machine. The axis control circuit 16 receives movement command amounts for the axes output by the processors 11 and outputs movement commands for the axes to the servo amplifier 17.

(19) Upon receiving the axis movement commands output by the axis control circuit 16, the servo amplifier 17 drives a servomotor 50.

(20) The servomotor 50 is driven by the servo amplifier 17 to move the motion axes of the machine. The servomotor 50 typically has a position/speed detector built-in. The position/speed detector outputs a position/speed feedback signal. Position/speed feedback control is performed as this position/speed feedback signal is fed back to the axis control circuit 16.

(21) In FIG. 1, the axis control circuit 16, servo amplifier 17, and servomotor 50 are each shown as being only one in number. Actually, however, these elements are provided corresponding in number to the axes of the machine to be controlled. In the case where a robot with six axes is controlled, for example, six sets, in total, of the axis control circuit 16, servo amplifier 17, and servomotor 50 may sometimes be provided corresponding individually to the axes.

(22) The control panel 60 is a data input/output device equipped with a display, hardware keys, and the like. The control panel 60 displays information received from the processors 11 through the interface 18 on the display. The control panel 60 delivers commands, data, and the like input from the hardware keys and the like to the processors 11 through the interface 18.

(23) FIG. 4 is a block diagram showing the schematic function and operation of the controller 1 according to the present embodiment. The controller 1 comprises a request message transmission and reception unit 101, sequence processing completion determination unit 102, ready message transmission and reception unit 103, and end message transmission and reception unit 104. The request message transmission and reception unit 101, sequence processing completion determination unit 102, ready message transmission and reception unit 103, and end message transmission and reception unit 104 may be implemented as one function of the processors 11 in hardware-wise. Moreover, the request message transmission and reception unit 101, sequence processing completion determination unit 102, ready message transmission and reception unit 103, and end message transmission and reception unit 104 may be implemented as the processors 11 execute programs stored the ROM 12, RAM 13, or non-volatile memory 14, for example.

(24) The processor 11a (processor #1) and the processor 11b (processor #2) of FIG. 4 manage their respective resources on the RAM 13. In the present embodiment, as shown in FIG. 10, the processors 11a and 11b independently manage different data (data #1 and #2) in one data set.

(25) The request message transmission and reception unit 101 transmits a request message from the processor 11a (arbitrary processor or core; processor #1 in FIG. 4) to the processor 11b (each of all the other processors or cores; processor #2 in FIG. 4). The processors 11a and 11b are in a one-to-many relationship.

(26) The request message is a message to the effect that backup processing is to be performed, which is notified to message recipients (processors 11b) by a sender (processor 11a). The request message includes information (index of a memory block) for specifying data (including the data sets) to be backed up.

(27) After the request message is transmitted, the request message transmission and reception unit 101 brings the processor 11a to an execution waiting state (standby state) for the backup processing.

(28) Upon receiving the request message, the processors 11b notify the sequence processing completion determination unit 102 of the contents of the request message.

(29) The sequence processing completion determination unit 102 determines whether or not sequence processing performed by the request message recipients (processors 11b) is completed. The sequence processing is processing related to the contents of the request message. Specifically, the processors 11b specify the data for access to the index of the memory block included in the request message and terminate the sequence processing related to the data.

(30) If the sequence processing is determined to have been completed, the sequence processing completion determination unit 102 sets the processors 11b to their standby state and transmits a notification to the ready message transmission and reception unit 103.

(31) The ready message transmission and reception unit 103 transmits ready messages from the request message recipients (processors 11b) to the request message sender (processor 11a).

(32) The ready messages are messages to the effect that part of processing related to the request message recipients (processors 11b), out of the sequence processing related to the backup processing performed by the request message sender (processor 11a), is completed, which are notified to the request message sender (processor 11a).

(33) The processor 11a determines whether or not the ready messages are received from all the processors 11b as destinations of the request messages. If the processor 11a concludes that the ready messages are received from all the processors 11b as the destinations of the request messages, the ready message transmission and reception unit 103 releases the execution waiting state (standby state) for the backup processing of the processor 11a.

(34) The processor 11a performs the backup processing.

(35) The end message transmission and reception unit 104 transmits an end message from the request message sender (processor 11a) to the request message recipients (processors 11b).

(36) The end message is a notification message to the effect that the backup processing is completed in the request message sender (processor 11a).

(37) The end message transmission and reception unit 104 releases the standby state of the processors 11b having received the end message.

(38) Advantages of the present embodiment over the prior art will be described with reference to FIG. 5. The sequence processing completion determination unit 102 as a constituent element of the present embodiment confirms that the sequence processing related to the data to be backed up in all the processors 11b having received the request messages is completed. Thereafter, the sequence processing completion determination unit 102 shifts the processors 11b to the standby state. If the processors 11b are shifted to the standby state immediately after receiving the request messages, inconsistency is inevitably caused between the data sets. In the present embodiment, however, the sequence processing completion determination unit 102 does not allow the processors 11b to shift to the standby state until the sequence processing ends and continues the sequence processing so that the data sets become consistent. Thus, inconsistency is not caused between the data sets.

(39) FIG. 6 is a chart showing an example of a processing flow between the processors in the case where the processors 11b (processors #2) execute data backup in the controller 1 in which a processor 11a (processor #1), processor 11b (processor #2), and processor 11c (processor #3) perform axis control of a system 1, axis control of a system 2, and axis control of a system 3, respectively.

(40) In an initial state, the processors 11a, 11b and 11c perform steps of processing related to the axis controls of the first, second, and third systems 1, 2 and 3, respectively (S11, S21 and S31).

(41) The processor 11b transmits request messages for backup processing to the processors 11a and 11c (S22). Thereafter, the processor 11b is set to the standby state.

(42) Upon receiving the request messages, the processors 11a and 11c complete sequence processing related to the contents of the request messages (S12 and S32). Thereafter, the processors 11a and 11c transmit ready messages to the processor 11b. Thereupon, the processors 11a and 11c are set to the standby state.

(43) If it is confirmed that the ready messages are received from all the processors 11a and 11c, the processor 11b releases the standby state and performs the backup processing (S23). When the backup processing is completed, the processor 11b transmits an end message to the processors 11a and 11c (S24). Moreover, the processor 11b resumes the execution of the axis control of the system 2 (S25).

(44) Upon receiving the end message, the processors 11a and 11c release the standby state and resume the execution of the axis controls of the systems 1 and 3 (S13 and S33).

(45) According to the present embodiment, even the controller 1 that frequently updates data and performs complicated access processing can perform data backup guaranteed with data integrity, data input/output, a shutdown sequence, and the like. Moreover, the present embodiment can avoid problems such as a reduction in performance due to overhead caused if a program for exclusive control is implemented, oppression of the storage or memory due to an increase in code quantity, and the like.

(46) Moreover, the present embodiment is configured so that the sequence processing is completed before the backup in a necessary range for the maintenance of the data integrity, in accordance with the contents of the request messages. In other words, the present embodiment is configured so that the backup processing is on standby until the completion of the sequence processing. Thus, the execution range of the sequence processing, that is, the guarantee range of the data integrity, is appropriately set according to the dependency between the systems or between control axes.

(47) In the embodiment described above, a series of processing steps is illustrated as being performed with the request messages for the backup processing as triggers. However, the types, forms, and contents of the request messages, the contents and range of the sequence processing, and the like may be different, depending on the type of processing performed by a primary processor or core. In the case where the backup processing is performed, for example, terms and conditions may be allowed to be appropriately changed depending on differences in aspects, such as backup for the non-volatile memory 14 and the ROM 12, backup to an external storage, and the like.

Embodiment 2

(48) The operation of a controller 1 according to Embodiment 2 will be described with reference to FIG. 7. Embodiment 2 is a modification of Embodiment 1. The constituent elements and operation of the controller 1 according to Embodiment 2 are the same as those of Embodiment 1 unless otherwise specified.

(49) In the present embodiment, a request message recipient (processor 11b in the case of Embodiment 1) is implemented with, as an alternative task, processing that does not depend on (or does not influence) processing (backup processing in the case of Embodiment 1) notified by a request message. After transmitting a ready message, the processor 11b performs the alternative task instead of shifting to the standby state. Specifically, the processor 11b continues to perform a task irrelevant to the backup processing in a memory space independent of the backup processing.

(50) Upon receiving an end message, in this case, the end message transmission and reception unit 104 determines whether the processor 11b is in a completion waiting state (standby state) for the backup processing or in a state in which the alternative task is being performed. If the processor 11b is in the completion waiting state (standby state) for the backup processing, the standby state is released. If the alternative task is being performed, in contrast, the task (e.g., axis control) having been being performed at the time of the request message reception is performed.

(51) According to the present embodiment, the processor or core having received the request message can perform the alternative task while it is waiting for the completion of requested processing, so that the processing efficiency of the entire controller 1 can be improved.

Embodiment 3

(52) The operation of a controller 1 according to Embodiment 3 will be described with reference to FIG. 8. Embodiment 3 is a modification of Embodiment 1. The constituent elements and operation of the controller 1 according to Embodiment 3 are the same as those of Embodiment 1 unless otherwise specified.

(53) In the present embodiment, completion determination conditions for sequence processing and operation after end message reception are changed depending on the types of messages transmitted from a primary processor.

(54) FIG. 8 is a chart showing the operations of a processor 11a (processor #1), processor 11b (processor #2), and processor 11c (processor #3) in the case where an operation scheme related to backup processing of Embodiment 3 is applied to a shutdown sequence upon the occurrence of a system error.

(55) In an initial state, the processors 11a, 11b and 11c perform steps of processing related to the axis controls of first, second, and third systems 1, 2 and 3, respectively (S211, 5221 and S231).

(56) The processor 11b transmits system error occurrence notifications (equivalent to the request messages for the backup processing of Embodiment 1) to the processors 11a and 11c (S222). The system error occurrence notifications are also assumed to include information related to an index of a memory block in which data to be backed up exists. Thereafter, the processor 11b is set to the standby state.

(57) Upon receiving the system error occurrence notifications, the processors 11a and 11c individually complete sequence processing related to the data to be backed up. The processors 11a and 11c may be configured to perform, at the time of reception of the system error occurrence notifications, processing for resetting a register, reducing the core frequency, or the like, to be ready for the execution of the shutdown sequence (S212 and S232). When the sequence processing and the like are completed, the processors 11a and 11c transmit ready messages to the processor 11b. Thereafter, the processors 11a and 11c are set to the standby state.

(58) If it is confirmed that the ready messages are received from all the processors 11a and 11c, the processor 11b releases the standby state and performs the shutdown sequence (S223). When the shutdown sequence is completed, the processor 11b transmits a processor stop request (equivalent to the end message of Embodiment 1) to the processors 11a and 11c (S224). Moreover, the processor 11b stops its operation (S225).

(59) Upon receiving the processor stop request, the processors 11a and 11c release the standby state and stop their operations (S213 and S233).

(60) While embodiments of the present invention have been described herein, the invention is not limited to the above embodiments and may be suitably modified and embodied in various forms.

(61) For example, the present invention is not limited to the data backup, data input/output, and shutdown sequence and is applicable to various uses. For example, the present invention is applicable to a method of communication between processors or cores upon the occurrence of a system error, an execution method for emergency stop processing for safely stopping a system, and the like. Moreover, the present invention can also be used as a method for initializing a specific memory on a memory map in resuming an application.