Method and a system for producing a semi-conductor module

Abstract

In a method for producing a semi-conductor module (10) comprising at least two semi-conductor chips (12, 14) and an interposer (20) which has electrically conductive structures (28) connecting the semi-conductor chips (12, 14) to one another, the interposer (20) is printed directly onto a first (12) of the semi-conductor chips. When the interposer (20) is printed on, the electrically conductive structures (28) are produced by means of electrically conductive ink (68). The second semi-conductor chip (14) is mounted on the interposer (20) such that the two semi-conductor chips (12, 14) are arranged one above the other and that the interposer (20) forms an intermediate layer between the two semi-conductor chips (12, 14).

Claims

1. A method of producing a semi-conductor module comprising at least two semi-conductor chips or wafers arranged one above the other, comprising the steps of: printing a freestanding metallic elevation onto a first contact side of a first one of the semi-conductor chips or wafers by means of electrically conductive ink, wherein the metallic elevation has the form of a bump and is produced by an aerosol jet printing method by printing multiple layers one over another, and mounting a second one of the semi-conductor chips or wafers on the first semi-conductor chip or wafer such that the two semi-conductor chips or wafers are arranged one above the other such that the metallic elevation electrically a second contact side of the second semi-conductor chip or wafer is effected by the metallic elevation, which the second contact side faces in the opposite direction to that of the first contact side of the first semiconductor chip or wafer.

2. The method according to claim 1, wherein the mounting of the second semi-conductor chip or wafer is effected by fusing of the elevation of the first semi-conductor chip or wafer onto the contact of the second semi-conductor chip or wafer such that a permanent connection is produced between the elevation and the contact of the second semi-conductor chip.

3. The method according to claim 1, wherein a second electrically conductive ink is printed onto the metallic elevation, such that an easily fusible metallic coating is produced on the elevation.

4. The method according to claim 1, wherein firstly an interposer is arranged on the first semi-conductor chip or wafer and the metallic elevation is produced on the upper side of the interposer.

5. The method according to claim 4, wherein electrically conductive structures of the interposer are produced by electrically conductive ink.

6. The method according to claim 1, wherein the electrically conductive ink for producing the metallic elevation is discharged from a nozzle.

7. The method according to claim 1, wherein the electrically conductive ink comprises metallic particles with a maximum dimension of at most 20 nm.

8. The method according to claim 1, wherein the electrically conductive ink comprises silver, gold and/or copper particles.

9. The method according to claim 1, wherein the electrically conductive ink comprises metallic particles which connect to one another at a temperature of below 200 C.

10. The method according to claim 1, wherein the electrically conductive ink comprises metallic particles which connect to one another when irradiated with light having a wavelength of less than 600 nm.

11. The method according to claim 1, wherein the metallic elevation is printed directly onto a metallic contact area of the first semi-conductor chip or wafer, and subsequently (i) electrically conductive structures of an interposer are connected with the metallic elevation, or (ii) a contact on the second contact side of the second semi-conductor chip or wafer is connected directly with the metallic elevation.

12. A semi-conductor module comprising: at least two semi-conductor chips or wafers arranged one above the other, and an interposer, which interposer comprises electrically conductive structures, in form of at least one wiring plane connecting the semi-conductor chips or wafers, the interposer being arranged directly on top of a first of the at least two semiconductor chip or wafer such that there is no gap between the interposer and the first semiconductor chip or wafer, the interposer including a plurality of individually printed layers, a first of the plurality of individually printed layers comprising (1) a first layer of electrically insulating material printed directly onto an upper side of the first of the semi-conductor chips and having openings corresponding to contact surfaces of the first of the semi-conductor chips, and (2) electrically conducting material printed into the openings; a second of the plurality of individually printed layers comprising (1) conductive structures extending from the electrically conducting material atop the first layer of electrically insulating material, and (2) a second layer of electrically insulating material printed atop the first of the plurality of individually printed layers and adjacent the conductive structures and a freestanding metallic elevation being arranged on the top most one of the plurality of individually printed layers, via which an electrical contacting to a contact on a rear side of a second one of the semi-conductor chips or wafers is effected, the metallic elevation being formed from electrically conductive ink.

13. The semi-conductor module according to claim 12, wherein a metallic coating formed of a second electrically conductive ink and arranged on the metallic elevation forms a permanent metallic connection to the contact on the rear side of the second semi-conductor chip or wafer.

14. The semi-conductor module according to claim 12, wherein the metallic elevation comprises metallic particles with a maximum dimension of at most 20 nm.

15. The semi-conductor module according to claim 12, wherein the metallic elevation comprises silver, gold and/or copper particles.

16. The semi-conductor module according to claim 12, wherein the metallic elevation comprises metallic particles, which connect to one another at a temperature of below 200 C.

17. The semi-conductor module according to claim 12, wherein the metallic elevation comprises metallic particles, which connect to one another upon irradiation of light having a wavelength of less than 600 nm.

18. The semi-conductor module according to claim 12, wherein the metallic elevation directly connects a metallic contact area of the first semi-conductor chip or wafer and connects the metallic contact area (i) via electrically conductive structures of an interposer, or (ii) directly with the contact on the rear side of the second semi-conductor chip or wafer.

19. The semi-conductor module according to claim 12, the metallic elevation having the form of a bump.

20. The semi-conductor module according to claim 19, the metallic elevation being produced by an aerosol jet printing method by printing multiple layers one over another.

21. A method of producing a semi-conductor module comprising arranging at least two semi-conductor chips or wafers one above the other separated by an interposer, the interposer being arranged directly on top of a first of the at least two semi-conductor chips or wafers such that there is no gap between the interposer and the first semi-conductor chip or wafer, the arranging including forming the interposer by printing a first of a plurality of individually printed layers of the interposer comprising (1) a first layer of electrically insulating material printed directly onto an upper side of a first of the semi-conductor chips and having openings corresponding to contact surfaces of the first of the semi-conductor chips, and (2) electrically conducting material printed into the openings; printing a second of the plurality of individually printed layers comprising (1) conductive structures extending in a wiring plane from the electrically conducting material atop the first layer of electrically insulating material, and (2) a second layer of electrically insulating material printed atop the first of the plurality of individually printed layers and adjacent the conductive structures, and printing a freestanding metallic elevation on the top most one of the plurality of individually printed layers, via which an electrical contacting to a contact on a rear side of a second one of the semi-conductor chips or wafers is effected, the metallic elevation being formed from electrically conductive ink.

22. The method of claim 21, the printing a second of the plurality of individually printed layers including printing the conductive structures using electrically conductive ink discharged by aerosol jet printing.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) The above and further advantageous features of the invention are illustrated in the following detailed description of exemplary embodiments according to the invention with reference to the attached diagrammatic drawings. These show as follows:

(2) FIG. 1 a sectional view of a semi-conductor module according to the invention having four semi-conductor chips arranged one above the other and connected by means of interposers,

(3) FIG. 2 a sectional view of a first functional unit of a system according to the invention for producing a semi-conductor module,

(4) FIG. 3 a sectional view of a second functional unit of the system according to the invention for producing a semi-conductor module,

(5) FIG. 4 a sectional view of a third functional unit of the system according to the invention for producing a semi-conductor module,

(6) FIG. 5 a top view of the upper side of a semi-conductor chip having metallic contact surfaces,

(7) FIG. 6 the semi-conductor chip according to FIG. 5 having an electrically insulating layer printed onto the upper side of said chip,

(8) FIG. 7 the electrically insulating layer according to FIG. 6 having openings filled with electrically conductive ink,

(9) FIG. 8 the electrically insulating layer according to FIG. 7 having electrically conductive structures printed on said layer,

(10) FIG. 9 the structure according to FIG. 8 having a further electrically insulating layer embedding the electrically conductive structures,

(11) FIG. 10 the structure according to FIG. 9 having further electrically conductive structures applied to the surface of said structure,

(12) FIG. 11 the structure according to FIG. 10 having further applied electrically insulating layers and elevations formed by means of electrically conductive ink, and

(13) FIG. 12 the structure according to FIG. 11 having contact metal applied to the elevations.

DETAILED DESCRIPTION OF EXEMPLARY EMBODIMENTS ACCORDING TO THE INVENTION

(14) In the exemplary embodiments described below elements which are similar to one another functionally or structurally are provided as far as possible with the same or similar reference numbers. Therefore, in order to understand the features of the individual elements of a specific exemplary embodiment, reference is made to the description of other exemplary embodiments or to the general description of the invention.

(15) In order to facilitate the description of the projection exposure tool a Cartesian xyz coordinate system is specified in the drawings from which the respective relative position of the components shown in the figures is clear. In FIG. 1 the y direction runs perpendicular to the plane of the drawing and away from the latter, the x direction to the right, and the z direction upwards.

(16) FIG. 1 shows a diagrammatic illustration of a semi-conductor module 10 according to the invention in a sectional view. This is a three-dimensionally integrated module in which a number ofin this case foursemi-conductor chips 12, 14, 16 and 18 are stacked one above the other. So-called interposers 20, 22 and 24 are respectively disposed between the semi-conductor chips. The interposers connect the respective adjacent semi-conductor chips to one another electrically. The interposer 20 connects the semi-conductor chips 12 and 14, the interposer 22 connects the semi-conductor chips 14 and 16, and the interposer 24 connects the semi-conductor chips 16 and 18. In the example illustrated the semi-conductor chip 18 located right at the top of the stack is in the form of a sensor, whereas the semi-conductor chips 16, 14 and 12 located below include various integrated circuits.

(17) The interposer 20 between the semi-conductor chips 12 and 14 has electrically conductive structures 28 which are embedded into an electrically insulating material 30. According to the invention, both the electrically insulating material 30 and the electrically conductive structures 28 are printed directly onto an upper side 13 of the semi-conductor chip 12, as described in detail below. The electrically conductive structures 28 are formed by means of electrically conductive ink and contact metallic contact surfaces 26 on the upper side 13 of the semi-conductor chip 12. On the upper side of the interposer 20 the electrically conductive structures 28 are provided at a number of points with elevations made of contact metal 34so-called bumps. These bumps contact the second semi-conductor chip 14 from the lower side of the latter at metallically filled microholes in the form of so-called vias 32. The filled vias 32 pass through the whole thickness of the semi-conductor chip 14. The individual vias are respectively contacted on their upper side either with a bonding wire 36 or electrically conductive structures 28 of the interposer 22. The structure of the interposers 22 and 24 is similar to the structure of the interposer 20 that has just been described.

(18) FIGS. 5 to 12 illustrate in detail the application of the interposer 20 to the upper side 13 of the semi-conductor chip 12 in an embodiment according to the invention. FIGS. 2 to 4 illustrate a system 50 used for this purpose for producing a semi-conductor module in an embodiment according to the invention. The system 10 according to the invention comprises a first printing unit 58 shown in FIG. 2, a second printing unit 64 shown in FIG. 3, and a mounting device 72 shown in FIG. 4. The aforementioned functional units can be partially or totally integrated into a single apparatus or also be designed respectively as separate units.

(19) As shown in FIG. 2, the system 50 comprises a wafer holding device 52 for holding a wafer 54 which comprises a plurality of semi-conductor chips 12. According to the embodiment illustrated the semi-conductor chips 12 are processed without previous separation, i.e. as part of the wafer 54. The wafer 54 is first of all aligned by means of a wafer aligner 56 centrally on the wafer holding device 52. As shown in FIG. 5, the individual semi-conductor chips 12 have on their upper sides 13 a passivation layer 38 and a number of circular metallic contact surfaces 26 passing through the passivation layer 38.

(20) In a first step of the production method in an embodiment according to the invention a layer 31 made of an electrically insulating material 30 is printed directly onto the upper side 13 of the semi-conductor chip 12, i.e. onto the passivation layer 38, in the form of a dielectricum using the screen printing method. The printing is implemented here such that the electrically insulating layer 31 has openings 40 in the region of the contact surfaces 26. In order to print on the layer 31, in the system 10 a print mask 60 illustrated in FIG. 2 is pushed over the wafer 54 by means of a displacing device 61. After the screen printing has taken place, the printed material is cross-linked by irradiating with UV light or heat. For this purpose the system 50 has an appropriate radiation source 62.

(21) The openings 40 are then filled with conductive ink 68, as shown in FIG. 7. Furthermore, part of the conductor paths 42 forming electrically conductive structures 28 are printed onto the electrically insulating layer 31, as shown in FIG. 8. This is implemented by means of the second printing unit 64 shown in FIG. 3. This comprises a nozzle 66 for separating out the conductive ink 68, for example by means of an aerosol printing method. Here the conductive ink is applied to the insulating layer 31 by means of a continuous jet. The electrically conductive ink 68 can be configured differently, as stated in the general part of the description. According to one embodiment the ink 68 has silver particles of nanometer size. After applying the ink 68 the latter is irradiated with light from the laser 70 in order to cross-link or sinter the silver particles. Alternatively, the conductive ink 68 can also be applied to the insulating layer 31 by the screen printing method.

(22) As shown in FIG. 9, the conductor paths 42 are then embedded in a further electrically insulating layer 31. Further printing processes follow in which further electrically insulating layers 31 and further conductor paths 42 are produced, as shown in FIGS. 10 and 11. As final production steps metallic elevations 33 are printed by means of conductive ink 68. The contact metal 34 is applied to these elevations in order to form the aforementioned bumps, as shown in FIG. 12.

(23) The further processing of the wafer 54 with the interposer 20 disposed on the latter from FIG. 12 can take place in different ways. According to a first embodiment the wafer 54 is now diced into the individual semi-conductor chips 12 by sawing. Next the semi-conductor chips 12 are arranged individually over a chip holding apparatus 74 according to FIG. 4, and the semi-conductor chip 14 is placed on the interposer 20 by means of a chip placing apparatus 76 in such a way that corresponding contact surfaces on the lower side of the chip 14 contact the contact metals 34 of the interposer 20. As a result the further interposers 22 and 24 and the further semi-conductor chips 16 and 18 are applied in the same way as in the method described above, and so the semi-conductor module 10 is completed.

(24) In one embodiment according to the invention the individual semi-conductor chips 12, 14, 16 and 18 are tested with regard to their electrical properties before the three-dimensional integration of the semi-conductor module. The test result provides accurate information on faulty regions on the chips. The test results are used on the one hand in order to totally separate out faulty chips, and on the other hand in order to configure the layout of the electrically conductive structures 28 within the interposers 20, 22 and 24 in an appropriate way. This takes place such that faulty regions of the chips are excluded from the electrical contacting. Thus, for example, one can deviate from a line connection between two chip segments lying directly over one another if one of these segments is faulty, and in fact the line connection is guided to an adjacent segment of the faulty segment.

(25) According to a further embodiment the wafer 54 with the interposer 20 printed onto it is not initially diced. Rather, a further wafer containing the chips 14 is placed on it so that the corresponding contact surfaces on the lower side of the chips 14 contact the contact metals 34 of the interposer 20. The printing of the interposer 22 then takes place over the entire surface of the wafer. The further chips 16 and 18 and the interposer 24 can then also be applied to the whole surface. Only then does dicing take place by sawing the wafer stack. In this case too the electrically conductive structures 28 are adapted to the electrical test results of the chips.

(26) In the following further exemplary embodiments of the invention are described. Many of the exemplary embodiments describe embodiments illustrated above in different words, and other exemplary embodiments supplement or extend these.

(27) The method according to the invention is intended to facilitate the stacking of electronic components (chips) into stacks in the 3D integration and contacting them electrically with one another. The method makes possible one or more wiring planes here which are called interposers. According to one embodiment here at least two different components are preferably applied by printing. Here one component takes on the function of a dielectric layer and the other component the function of an electric conductor. By selective control of a printer it is possible to design the interposer to print such that the contacts of two different chips can be contacted with one another flexibly and individually.

(28) The following method largely dispenses with lithographic processes. It can be applied both to whole wafers and also to chips which have already been separated or to a combination of the latter.

(29) Upon the basis of the surface of a completely processed chip which can still be in the composite of a non-diced wafer or which is already separated, this wafer or chip is now optically recognised and mechanically aligned in an apparatus. On the surface of the chip there are surfaces which are mostly protected with an appropriate layer for the purpose of the structures lying beneaththe person skilled in the art talks of these being passivated. Moreover, on the chip there are surfaces which are open for the purpose of subsequent contactabilitythe mostly metallic surface of which has deliberately not been isolated.

(30) In the same apparatus which has aligned the wafer or the already separated chip there are according to one embodiment at least two print heads which can be controlled individually. However, these print heads can also be nozzles or other apparatuses which serve to apply material with low or high viscosity selectively and locally, such as for example screen printing devices.

(31) The first print head is now set in operation. It now moves away from those regions which should continue to remain isolated and prints on a liquid. Depending on the application this liquid can be a polyamide, a lacquer, a resin or some other organic or inorganic material, and is enrichedif necessarywith additives or other appropriate admixtures in order to optimise them as regards their viscosity and/or their subsequent dielectric, mechanical and geometric properties. By means of an appropriate method this liquid is now cross-linked or hardened to form a layer which has dielectric properties. This method can consist of hardening the printed on material by means of energetic radiation in the form of light, e.g. a lamp or a laser. The person skilled in the art is familiar with methods wherein lacquers are cross-linked by means of UV light. By means of the prompt cross-linking, drying or other solidification or hardening of the printed on liquid the latter should be prevented from running undesirably. By controlling the print head appropriately, such as for example its forward speed, its printing frequency or printing quantity, it can also be used to level out or to smooth the topography of the surface of the chipand so also that of a wafer. Indentations in the surface of the chips can thus be selectively filled.

(32) Today's printing techniques allow a wide bandwidth of different viscosity, and so even pasty materials can be printed.

(33) After the first print head has now printed on the liquid and has cross-linked, dried or solidified or hardened this appropriately in some other way, there remains a dielectric layer which has openings at points which are used for the purpose of contacting the chip or the wafer.

(34) A second print head is now set in operation which prints a metallically enriched or filled liquid which is also called electrically conductive ink. This ink can also be enriched selectively with additives for the purpose of its viscosity and subsequent mechanical, electrical or topographical properties.

(35) The printer with the metallic ink now selectively controls the surfaces which have not been printed with the dielectric material. By means of appropriate methods this ink is now treated so that it hardens and a good electrical connection with the metallic contact surfaces is reliably established. This can be a method which solidifies the ink by drying, for example in that solvent or water escapes. However, it is also possible to sinter or to fuse this ink by means of lasers or other appropriate energetic and/or thermal methods. It is not absolutely necessary here for the geometric properties of the metal printed in this way to be similar to that of the applied dielectric layer. By selective control of the print head the print result can also be optimised by means of the print speed or the print head setting and be adapted so that the print result of both materials is supplemented geometrically.

(36) According to one embodiment this first printed layer made of metal can also first of all be applied with another print head which prints a metallic ink which can contact and/or fuse better, by means of which the metallic connection to the contact surfaces is facilitated or improved, and only then printed with another metallic ink.

(37) After a first metallic layer has been applied to the contacts of the wafer or the chip the print head prints on one or further layers which are appropriately dried, sintered, cross-linked or solidified or hardened in some other way. Moreover, it now also prints conductor paths which are used for the subsequent rewiring. The print head is moved here one or more times such that a conductor path is produced. As regards its geometric design, this conductor path will correspond to the width, height and cross-section of the set requirements. It is likewise with regard to the electrical properties, conductivity and ohmic resistance.

(38) In the interplay between the two print heads one or more wiring planes can now be created. It can also be possible here for the two print heads, simultaneously or offset in time, to apply and cross-link or sinter their material to be printed.

(39) By the interplay between the two print heads it is thus possible for the different wirings to be moved such that they cross and nevertheless are isolated from one another by the printed dielectric layer.

(40) As a result a three-dimensional interposer is produced which is largely made of dielectric material and in which the electric wiring is contained.

(41) Methods are known wherein electronic components which are mostly passive for printing such as electric resistors or capacities are printed. Within the layer composite such components can be printed by such a method. Here the conductor paths produced with the conductive material will contact these components. With the method it is therefore also possible to implement such components between two chips or also to supplement the electrical function of an individual chip by such a component being implemented between two contacts of a single chip.

(42) For the purpose of the electrical contacting of the contacts on the rear side of the wafer or chip lying at the top it is possible by means of the print head to produce for the metallic ink a metal elevation which comes very close to the purpose and the form of a classic so-called bump. For this purpose the print head prints multiple layers one over another until an appropriate elevation has been achieved which facilitates electrical contacting to the contacts on the rear side of the wafer or chip lying on top of the latter.

(43) Moreover, it is possible for a third print head to print a second metallically filled ink onto the elevation which with regard to its thermal or other property facilitates contacting to the contact surfaces on the rear side. A metal coating is thus produced on the bump which would be able to fuse more easily.

(44) One advantage of the invention is the fact that one can dispense with lithographic methods, and so masks which are expensive and complex to produce do not have to be used either. In particular when producing small series or in single unit production considerable cost advantages are to be anticipated in comparison to conventional methods. The fact that the printer control alone constructs the interposer is a particular advantage here because adaptation and implementation of the requirements is only based upon the changing of files in which the respective interposer scheme is stored.

(45) It is a further advantage that components (chips) which have already been separated can be processed. Until now this was only possible very unsatisfactorily because until now the conventional lithographic methods were mostly only applicable to non-diced wafers.

(46) Moreover, the flexible configuration of the interposer makes it possible to connect very many basic components (chips) of totally different size, geometric design and function to one another and to guarantee adaptable wiring within the resulting stack. A further advantage is that passive components can also be placed within the interposer.

(47) A chip that has already been sawn from a wafer and so has been separated (semi-conductor component) should be stacked with a further separated chip and be electrically contacted. Both of these chips are components with different functions and different geometric designs. At least the chip at the top has been substantially thinned and for the purpose of electrical signal guiding has contacts on the rear side of the chip which by means of metallically filled holes (so-called vias) in the chip enable contacting from the front side of the chip to its rear side.

(48) The chip lying at the bottom is aligned on the front side by means of optical recognition within a printing device. A print head now starts to apply a lacquer which is cross-linked within a second by means of a light beam with a high proportion of UV guided synchronously to the print head. By means of the light the previously applied lacquer is cross-linked here so that conversion to a solid material which has dielectric properties takes place.

(49) By directing the print head and the synchronously guided light beam there is now produced on the component a layer with a dielectric property which has openings at previously determined points to which this layer is not applied. At these points are located contact surfaces of the chip which are kept free for the purpose of contacting.

(50) Next a further print head applies a metallically filled liquid (metallically filled ink) selectively to those free points which have been previously omitted in the production of the dielectric layer and so have been kept free. A laser which this time cross-links or sinters the metallic filling of the liquid by means of its energy is directed synchronously here.

(51) After the open contacts have been filled with the metallic ink, the print head is now controlled such that conductor paths are produced. By appropriately controlling both print heads an interposer is now constructed which guides the conductor paths contained within it such that the desired electrical contacting of both chips takes place. Here the conductor paths are embedded into the insulating material such that undesired contacting of the latter with one another or with the respective chips does not take place.

(52) The invention includes the aspects described in the following clauses. These clauses form part of the description and are not claims.

(53) Clause 1: A method wherein an interposer is produced by printing between stacked chips and/or wafers and microelectronic elements.

(54) Clause 2: The method according to Clause 1 wherein this interposer is made of at least one insulating and/or one electrically conductive component.

(55) Clause 3: The method according to either of the preceding clauses wherein the insulating layer is applied by printing.

(56) Clause 4: The method according to any of the preceding clauses, wherein the insulating layer is applied by means of rotation coating, spray coating, dispensing and/or by means of a nozzle.

(57) Clause 5: The method according to any of the preceding clauses, wherein the insulating layer is made of organic or inorganic material or a mixture of the latter.

(58) Clause 6: The method according to any of the preceding clauses, wherein the insulating layer is enriched with fillers and/or additives.

(59) Clause 7: The method according to any of the preceding clauses, wherein the insulating layer is hardened after printing.

(60) Clause 8: The method according to any of the preceding clauses, wherein the insulating layer is cross-linked and/or hardened by means of actinic radiation, chemical reaction, heat or drying after printing.

(61) Clause 9: The method according to any of the preceding clauses, wherein the insulating layer is applied such that it levels out or smoothes the topography of a surface.

(62) Clause 10: The method according to any of the preceding clauses, wherein the insulating layer is applied such that specific regions remain free of said layer.

(63) Clause 11: The method according to any of the preceding clauses, wherein the surfaces remaining free are produced by the applied material not being cross-linked or being selectively removed again at these points.

(64) Clause 12: The method according to any of the preceding clauses, wherein the electrically conductive material is applied by means of printing methods.

(65) Clause 13: The method according to any of the preceding clauses, wherein the electrically conductive material is made of a metallically filled or enriched liquid.

(66) Clause 14: The method according to any of the preceding clauses, the metallically filled or enriched liquid being cross-linked, dried or hardened by means of heat, light or lasers and having an electrically conductive function.

(67) Clause 15: The method according to any of the preceding clauses, the metallically filled or enriched liquid being applied to the surfaces omitted by the insulating layer or to free surfaces and/or being embedded in the insulating layer.

(68) Clause 16: The method according to any of the preceding clauses, the printing method applying the metallically filled or enriched liquid so that by printing a number of times a three-dimensional structure is produced which after cross-linking, drying, fusing or sintering makes it possible to produce wiring selectivelyeven multi-layeredeven crossingeven mergingfrom the conductive component in three-dimensional alignment.

(69) Clause 17: The method according to any of the preceding clauses, the conductive component and the insulating component being produced simultaneously, one after the other or in a specific sequence so as to produce a three-dimensional layer here which has dielectric properties, but has selectively metallic structures in the form of conductor paths in order to make possible and to guide electric contacts.

(70) Clause 18: The method according to any of the preceding clauses, by means of the vertical structure the conductive component constituting a metallic contact projecting out of the interposer and which fulfils the function of a bump and which should enable easier contacting.

(71) Clause 19: The method according to any of the preceding clauses, the contact projecting out being able to be covered by a second conductive component.

(72) Clause 20: The method according to any of the preceding claims, the dielectric component protecting the contacts from the conductive component guided within it or to the outside from undesired contacts.

(73) Clause 21: The method according to any of the preceding clauses, the interposer being applied to a wafer and/or chip, and being used for electrical contacting or rewiring between wafers and/or chips and/or sensors and/or MEMS.

(74) Clause 22: The method according to any of the preceding clauses, a chip and/or a wafer being optically recognised and mechanically aligned before applying the interposer.

(75) Clause 23: The method according to any of the preceding clauses, an electrical component being applied when producing the interposer by means of a printing method.

(76) Clause 24: The method according to any of the preceding clauses, a passive electrical component being applied when producing the interposer by means of placing and/or printing.

(77) Clause 25: The method according to any of the preceding clauses, when producing the interposer a contact being produced which can be contacted on the side of the interposer.

(78) Clause 26: The method according to any of the preceding clauses, the interposer first of all being printed on a surface which is neither a wafer nor a chip, and only being introduced between the wafer and/or the chip after it has been completed.

(79) Clause 27: The method according to any of the preceding clauses, the interposer selectively having good thermal conductivity.

(80) Clause 28: The method according to any of the preceding clauses, the interposer being used for heat dissipation and/or being thermally contactable.

(81) Clause 29: The method according to any of the preceding clauses, the conductive component also being applied by means of imprinting.

(82) Clause 30: A device for implementing the method according to any of the preceding clauses and which has at least two print heads.

(83) Clause 31: The device according to any of the preceding clauses, having one or a number of apparatuses for optically recognising, aligning wafers and/or chips and for printing, cross-linking, drying, sintering or fusing the applied components.

LIST OF REFERENCE NUMBERS

(84) 10 semi-conductor module 12 semi-conductor chip 13 upper side 14 semi-conductor chip 16 semi-conductor chip 18 semi-conductor chip 20 interposer 22 interposer 24 interposer 26 metallic contact surface 28 electrically conductive structures 30 electrically insulating material 31 electrically insulating layer 32 filled via 33 metallic elevation 34 contact metal 36 bonding wire 38 passivation layer 40 opening 42 conductor path 50 system for producing a semi-conductor module 52 wafer holding device 54 wafer 56 wafer aligner 58 first printing unit 60 print mask 61 displacing device 62 radiation source 64 second printing unit 66 nozzle 67 displacing device 68 electrically conductive ink 70 laser 71 displacing device 72 mounting device 74 chip holding apparatus 76 chip placing apparatus