Abstract
A Display system driven with binary pulse-width-modulation requires very high data transfer rate to achieve high grayscale. This invention discloses the embodiments of hardware structures and configurations which enable to reduce substantially the data transfer rate using non-sequential order of binary bits, wherein the combination of the sequences of binary bits is selected from the combinations which avoid simultaneous writing of multiple rows. The implementation of this invention substantially reduces the power consumption and the number of connecting pads of display chip
Claims
1. An image display system having a plurality of pixel elements to receive and apply digital image data of multiple bits to display image according to the digital image data, the image display system further comprising: a controller to control a process of writing the digital image data into each of the pixel elements by dividing the image data of multiple bits into a plurality of groups and writing each group of bits into the pixel element in a non-sequential order that is unrelated to a significance order of bit, neither in an order of from a most significant bit (MSB) to a least significant bit (LSB) nor from the LSB to the MSB, and without a writing conflict in writing said memory data into two pixel elements simultaneously during a process of writing and a look up table containing at least one set of sequences of data writing for said display system.
2. The image display system of claim 1 wherein: said look up table comprises look-up data stored in a non-volatile memory.
3. The image display system of claim 2 wherein: said look up table is separate from display device
4. The image display system of claim 1 wherein: said look up table is embedded inside display device
5. The image display system of claim 1 wherein: the display controller and look-up-table are included as an integrated part of the display device
6. The image display system of claim 1 wherein: the pixel elements in each of the rows are divided into groups including interleaved lines
7. An image display system having a plurality of pixel elements to receive and apply digital image data of multiple bits to display image according to the image data, the image display system further comprising: a controller to control a process of writing the image data into each of the pixel elements by dividing the image data of multiple bits into groups and writing each group of bits into the pixel element in a non-sequential order of significance of bit, neither in an order of from a most significant bit (MSB) to a least significant bit (LSB) nor from the LSB to the MSB, and without a writing conflict in writing said memory data into two pixel elements simultaneously during the process of writing and high significance bits including MSB are subdivided into at least two units.
8. The image display system of claim 7 wherein: a look up table containing data defining at least one set of sequences of writing the image data for said display.
9. The image display system of claim 7 wherein: the pixel elements in each of the rows are divided into groups including interleaved lines.
10. An image display system having a plurality of pixel elements to receive and apply digital image data of multiple bits to display image according to the image data, the image display system further comprising: a controller to control a process of writing the image data into each of the pixel elements by dividing the image data of multiple bits into groups and writing each group of bits into the pixel element in a non-sequential order of significance of bit, neither in an order of from a most significant bit (MSB) to a least significant bit (LSB) nor from the LSB to the MSB, and without a writing conflict in writing said memory data into two pixel elements simultaneously during the process of writing; and said controller is made of FPGA.
Description
BRIEF DESCRIPTION OF THE FIGURES
[0010] FIG. 1 shows High Definition (HD) display pixel array having 1920 columns and 1080 rows.
[0011] FIG. 2 shows the conventional technology that writes pixel memories in a sequential order for both spatial and temporal orders, wherein the pixels in a column will be written from row 1 through row 1080 (spatial sequential order) and MSB (most significant bit) through LSB (least significant bit).
[0012] FIG. 3 shows an example of digital image data that represents 10101001 in 8 bit binary code or 169 in decimal.
[0013] FIG. 4 shows that the actual writing time is very limited in spite of plenty of non-writing time, the speed required to write these signals is extremely high, because of the concentration of writing signals in a short period to write LSB.
[0014] FIG. 5 shows method of sequential writing as illustrated wherein all the pixels in a column have to be written within a LSB period so that the next data can be written right after LSB.
[0015] FIG. 6 shoes the use of non-sequential order of image data writing of this invention that uses both spatial and temporal non-sequential order and instead of writing full rows in a sequence, after writing MSB data for partial rows, the system returns to the first row and write the 2.sup.nd MSB thus reducing the LSB time substantially.
[0016] FIG. 7A shows an example of sequential data writing. FIG. 7B is an example of non-sequential data writing. FIG. 7C shows an example to write both the datum in FIG. 7A and FIG. 7B are written in the same time period.
[0017] FIG. 8 shows an embodiment of this invention with non-sequential writing with reduced artifacts by reducing the MSB time unit by half.
[0018] FIG. 9 shows an example of embodiments of this invention, display device (101) and controller (105) having a look up table (107) containing a sequence of data writing based on this invention.
[0019] FIG. 10 illustrates an example of this invention wherein display device (101) containing a look up table (107) internally.
[0020] FIG. 11 illustrates an example of this invention wherein a look up table (107) is included in a display controller (105), which receives signal data and transfer the signal data to the display device.
[0021] FIG. 12 illustrates an example of this invention wherein a look up table (107) and display controller (105) are included in a display device (101).
[0022] FIG. 13 illustrates an example of this invention wherein a look up table (107) and display controller (105) and frame memory(108), which memorizes the incoming video signal data, are included in a display device.
[0023] FIG. 14 illustrates a comparison between conventional data writing sequence and this invention's sequence.
[0024] FIG. 15 illustrates a comparison among various types of data writing. The conventional model using sequential data writing shows high power consumption and the models incorporating this method show dramatic power reduction.
[0025] FIG. 16 illustrates a comparison among various types of data writing. The conventional model using sequential data writing shows high number of IC pads as well as high power consumption and the models incorporating this method show dramatic reduction of power consumption and the number of IC pads.
[0026] FIG. 17 shows an actual projected image created by a device implementing a method of this invention that uses non-sequential algorism. No artifacts in the image are noticeable.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
[0027] A display device (101) has a pixel array (102) as in FIG. 9. For example, if it is a HDTV, the array has 1920(horizontal)1080(vertical) pixels in an array. Each pixel consists of a device which either emits light (plasma, OLED) or reflect light (LCOS, micromirror) or modulate light (LCD) to create images. A display device usually has a set of column drivers and row drivers. The column drivers send video signal to pixels in the row which a row driver selects. The signals sent by the column drivers will be transferred to pixels in the row. The system selects only one row at a time assuming there is no duplicated image in the display. The controller (105) in FIG. 9 controls which row should be chosen through sequencer (106) and transfer signals to the pixels in the row. The pixels which received the signals will either emits light (plasma, OLED) or reflects light (LCOS, micromirror) or modulate light (LCD) according to the signals. Because the incoming signals to the Image Signal unit (109) is sequential from top row to bottom row, the display controller also sends signals from top row to bottom row. The incoming signals are often in 3 colors parallel as HDMI and VGA. Depending on the type of display, it may require 3 colors parallel or each color sequential. If the display is a color sequential display, it requires each color sequentially. The timing of incoming signals and the timing of writing signals into pixels often do not match. There is a need of frame memory (108) storing the incoming signals to adjust timing and/or sequence of signals between incoming signals and display device. On top of these, this invention requires a memory which stores the sequence of rows and the orders of data bits to write signals into pixels. We call this memory Look-Up-Table(LUT) as (107) in FIG. 9. The sequence of row and data bits has to be stored in the LUT.
[0028] FIG. 7A, B and C illustrate an example showing a sequential writing (FIG. 7A) and a non-sequential data writing in time domain (temporal non-sequential order of data writing, FIG. 7B) and both writings are implemented in a same period (FIG. 7C). Typical order to write data is from MSB through LSB as FIG. 7A and FIG. 7B is an example of non-sequential. FIG. 7A shows the timing of data writing. 201 is the time to write D0 (MSB) and 204 is the time to write D1 and 205 is the time to write the end of LSB. FIG. 7B shows an example to write the video data (D0 through D7) in non-sequential order. Assuming that the system will write video data in the upper half of pixel array in the order of FIG. 7A and write data in the lower half of pixel array in the order of FIG. 7B, it can be shown that both the datum in FIG. 7A and FIG. 7B can be written during the same time period. In the upper half of the pixel array, the first data is written at 201 then the second data is written at 204. The time period between 201 and 204, no data is written into the upper array. This means that the bit lines are available to write data into the lower array. As shown in FIG. 7B, the data D3(202), D4(203), D5,D7 and D6 in FIG. 7B can be written before the next time (204) to write data into the upper array. Thus, both upper and lower halves of array can be written during the same time period. This means that the entire pixel array can be written in half time of sequential order. If we divide the entire array into N blocks and if we can write data into each block without conflicts, the entire array can be written in 1/N of time period of the conventional sequential writing. This means that we can transfer N times more data within the same time period. This is the basic principle of this algorism (we named this algorism High Speed Video Data Transfer or HSVT). To enable this, we need to write rows in non-sequential order (Spatial Non-Sequential Order), because we switch rows between the upper and the lower array.
[0029] FIG. 9 illustrates an example of embodiments using an external controller chip (105), a Look-Up-Table(LUT), a frame memory(108) and a unit (109) to receive incoming signal and transfer to the controller. The image signal unit (109) transfers incoming signal to the controller (105). The signal must be digital. If the incoming signal is analog such as VGA, the signal must be converted to digital. If the signal is digital as HDMI or DVI, these can be stored in the frame memory (108) . As described before, the incoming timing of each signal often does not match the need by the display device (101). This problem can be resolved by adding a frame memory which stores the entire data of frame(s), so that the display controller can adjust timing of data transfer to the display device (101).
[0030] FIG. 10 illustrates an example of embodiments using an external controller chip (105), an external frame memory and an internal look-up-table which resides inside the display device. This will reduce the burden of the display controller (105).
[0031] FIG. 11 illustrates an example of embodiments using an external controller chip (105), wherein a look-up-table is embedded inside the controller.
[0032] FIG. 12 illustrates an example of embodiments using an external controller chip (105), wherein a look-up-table is embedded inside the controller.
[0033] FIG. 13 illustrates an example of embodiments using an internal controller chip (105), internal look-up-table (107), an internal frame memory and internal sequencer inside the display device.
[0034] Although the present invention has been described in terms of the presently preferred embodiment, it is to be understood that such disclosure is not to be interpreted as limiting. Various alternations and modifications will no doubt become apparent to those skilled in the art after reading the above disclosure. Accordingly, it is intended that the appended claims be interpreted as covering all alternations and modifications as fall within the true spirit and scope of the invention.
