Semiconductor device along with multi-functional units and method for manufacturing a semiconductor device

Abstract

A semiconductor component includes at least two functional units which are identical to one another and are wired to one another, the identical functional units each include at least one gate finger, at least one source finger and at least one drain finger; the wiring comprising conductor tracks. A first track connects the gate fingers respectively, a second track connects the source fingers respectively, and a third track connects the drain fingers of the at least two same functional units, respectively.

Claims

1. A semiconductor device, comprising: at least two functional units that are identical to each other and wired to each other, wherein a wiring between the at least two functional units includes conductor tracks, each of the at least two functional units includes at least one gate finger, at least one source finger, and at least one drain finger, and a first one conductor track of the conductor tracks interconnects each of the at least one gate finger, a second conductor track of the conductor tracks interconnects each of the at least one source finger, and a third conductor track of the conductor tracks interconnects each of the at least one drain finger of the at least two functional units.

2. The semiconductor device according to claim 1, wherein each of the at least two functional units comprises at least two gate fingers, at least two source fingers and at least two drain fingers.

3. The semiconductor device according to claim 1, wherein each of the at least one gate finger includes a gate contact area, each of the at least one source finger includes a source contact area and each of the at least one drain finger includes a drain contact area.

4. The semiconductor device according to claim 3, wherein the first conductor track of the conductive tracks, the second conductor track of the conductive tracks, and the third conductor track of the conductive tracks interconnect the at least two functional units via the gate contact area, the source contact area, and the drain contact area, respectively.

5. The semiconductor device according to claim 4, wherein the first conductor track, the second conductor track, and the third conductor track of the conductor tracks interconnect the at least two functional units via the gate contact area, the source contact area, and the drain contact area in an electrically conductive manner.

6. The semiconductor device according to claim 3, wherein the gate contact area, the source contact area and the drain contact area of the two identical functional units are arranged such that an imaginary straight line drawn in one direction in each contact area, which imaginary straight line interconnects all contacts of a respective terminal type, without contacting any of another terminal type being intersected by the imaginary straight line.

7. The semiconductor device according to claim 1, wherein the first conductor track of the conductor tracks, the second conductor track of the conductor tracks, and the third conductor track of the conductor tracks are rectilinear.

8. The semiconductor device according to claim 1, comprising at least five functional units that are identical to each other.

9. The semiconductor device according to claim 1, wherein the at least two functional units are arranged in a grid directly adjacent to each other.

10. The semiconductor device according to claim 3, wherein the first conductor track of the conductor tracks interconnects the gate contact area of all of the at least one gate finger, the second conductor track of the conductor tracks interconnects the source contact area of all of the at least one source finger, and the third conductor track of the conductor tracks interconnects the drain contact area of all of the at least one drain finger of the at least two functional units.

11. The semiconductor device according to claim 3, wherein the first conductor track of the conductor tracks does not contact one gate contact area, the second conductor track of the conductor tracks does not contact one source contact area, and/or the third conductor track of the conductor tracks does not contact one drain contact area.

12. The semiconductor device according to claim 11, wherein the at least one gate finger is short-circuited to the at least one source finger of one of the at least two functional units.

13. The semiconductor device according claim 1, wherein the at least two functional units are transistors.

14. The semiconductor device according to claim 13, wherein the at least two functional units are GaN high electron mobility transistors (HEMT).

15. A transistor comprising the semiconductor device according to claim 1.

16. The transistor of claim 15, wherein the semiconductor device is a GaN HEMT.

17. The semiconductor device according to claim 1, wherein semiconductor dies on a carrier are physically separate from each other, and each of the semiconductor dies includes the at least one gate finger, the at least one source finger, and the at least one drain contact finger on an upper surface thereof.

18. A semiconductor device, comprising: a plurality of semiconductor dies on a carrier that are physically separate from each other and each includes two functional units that are identical to each other and wired to each other, wherein a wiring between the two functional units includes conductor tracks, each of the two functional units further includes a gate finger, a source finger, and a drain finger, a first conductor track of the conductor tracks interconnects the gate finger, a second conductor track of the conductor tracks interconnects the source finger, and a third conductor track of the conductor tracks interconnects the drain finger of the two functional units, and the plurality of semiconductor dies include gate, source, and drain contact fingers on an upper surface thereof.

19. The semiconductor device according to claim 18, wherein each of the two functional units includes two gate fingers, two source fingers, and two drain fingers.

20. The semiconductor device according to claim 18, wherein each of the gate finger includes a gate contact area, each of the source finger includes a source contact area, and each of the drain finger includes a drain contact area.

21. The semiconductor device according to claim 20, wherein the first conductor track of the conductive tracks, the second conductor track of the conductive tracks, and the third conductor track of the conductive tracks interconnect the at least two functional units via the gate contact area, the source contact area, and the drain contact area, respectively.

22. The semiconductor device according to claim 20, wherein the first conductor track, the second conductor track, and the third conductor track of the conductor tracks interconnect the two functional units via the gate contact area, the source contact area, and the drain contact area in an electrically conductive manner.

23. The semiconductor device according to claim 22, wherein the gate contact area, the source contact area and the drain contact area of the two identical functional units are arranged such that an imaginary straight line drawn in one direction in each of the gate contact area, the source contact area, and the drain contact area, wherein the imaginary straight line interconnects all contacts of a respective terminal type (gate, source, drain), without contacting any of another terminal type being intersected by the imaginary straight line.

24. The semiconductor device according to claim 18, wherein the first conductor track of the conductor tracks, the second conductor track of the conductor tracks, and the third conductor track of the conductor tracks are rectilinear.

25. The semiconductor device according to claim 18, comprising at least five functional units that are identical to each other.

26. The semiconductor device according to claim 18, wherein the two functional units are arranged in a grid directly adjacent to each other.

27. The semiconductor device according to claim 20, wherein the first conductor track of the conductor tracks interconnects the gate contact area of the gate finger, the second conductor track of the conductor tracks interconnects the source contact area of the source finger, and the third conductor track of the conductor tracks interconnects the drain contact area of the drain finger of both of the two functional units.

28. The semiconductor device according to claim 20, wherein the first conductor track of the conductor tracks does not contact one gate contact area, the second conductor track of the conductor tracks does not contact one source contact area, and/or the third conductor track of the conductor tracks does not contact one drain contact area of the two functional units.

29. The semiconductor device according to claim 28, wherein the gate finger is short-circuited to the source finger of one of the two functional units.

30. The semiconductor device according claim 18, wherein the two functional units are transistors.

31. The semiconductor device according to claim 30, wherein the two functional units are GaN high electron mobility transistors (HEMT).

32. A transistor comprising the semiconductor device according to claim 18.

33. The transistor of claim 32, wherein the semiconductor device is a GaN HEMT.

Description

INTRODUCTION TO THE FIGURES

(1) The embodiments of the invention are illustrated by examples, however, not in a way that transfers or incorporates limitations from the Figures into the patent claims. Same reference numerals in the Figures denote same elements.

(2) FIG. 1 shows first functional units 2 on a first semiconductor wafer;

(3) FIG. 2 shows printed functional units that are wired to each other on a second semiconductor wafer, as a semiconductor device 50;

(4) FIG. 3 shows first (unwired) functional units 2 on a first semiconductor wafer;

(5) FIG. 4 shows printed functional units that are wired to each other on a second semiconductor wafer, as a semiconductor device 50.

DETAILED DESCRIPTION OF THE FIGURES

(6) FIG. 1 shows functional units 2 that are identical to each other and arranged on a first semiconductor wafer in an array (grid) consisting of three times four functional units 2.

(7) The functional units 2 on the first semiconductor wafer are arranged lying in a plane.

(8) The array or grid in which the functional units 2 are arranged is congruent with the plane spanned by a surface of the functional units 2. The coordinates can be clearly defined by an x-y coordinate system. The functional units 2 are of a rectangular basic shape.

(9) A detailed view of a functional unit 2 is shown in FIG. 1, from which it is apparent that the functional unit 2 comprises three gate fingers 16, two source finger 17 and one drain finger 18 that have an elongate (finger-like) extension. The functional unit 2 comprises further gate fingers 16, further source fingers 17 and further drain fingers 18 (not shown).

(10) Each functional unit 2 can be transistor, especially a GaN HEMT.

(11) Each functional unit 2 can preferably comprise at least two gate fingers 16, at least two source fingers 17 and/or at least two drain fingers 18.

(12) The gate fingers 16, source fingers 17 and drain fingers 18 can be of a rectangular basic shape, wherein the width-to-height ratio is preferably less than 1:4 (width to height or height to width), particularly preferably less than 1:8.

(13) The distances between the individual gate, source and drain fingers 16, 17, 18 differ in size. The distance d.sub.1 between the drain finger 18 and the gate finger 16 arranged adjacent thereto is greater than the distance d.sub.2 between the gate finger 16 and the source finger 17 arranged adjacent thereto (d.sub.1>d.sub.2).

(14) The distances d.sub.1 from the drain finger 18 to the gate fingers are each equal in size. The same applies to the distances d.sub.2 between the gate fingers 16 and the source fingers 17.

(15) The functional units 2 are separated from each other by a trench 4.

(16) The trench 4 can be required for a previous manufacturing process of the functional units 2, especially for free etching thereof.

(17) A distance d.sub.3 is the distance between the functional units 2 as seen in the x direction (width of the trench 4 in the x direction).

(18) A distance d.sub.4 is the distance between the functional units 2 as seen in the y direction (width of the trench 4 in the y direction).

(19) The distances d.sub.3, d.sub.4 can differ in size.

(20) Each functional unit 2 comprises one gate contact area 6, one source contact area 7 and one drain contact surface 8.

(21) The gate contacts 6 can be of a square basic shape. The source contact areas 7 and the drain contact areas 8 can be of a rectangular basic shape.

(22) According to the terminal type (gate, source, drain), the gate fingers 16, source fingers 17 and drain fingers 18 can be wired to each other within one functional unit 2.

(23) The gate contact area 6, source contact area 7 and drain contact area 8 of the functional unit 2 can especially be electrically contactable.

(24) A plurality of functional units 2 can be arranged on the semiconductor wafer, preferably more than one hundred identical functional units 2.

(25) FIG. 2 shows a semiconductor device 50 on a second semiconductor wafer. The semiconductor device 50 comprises three wired functional units 2 that are wired or connected to each other via conductor tracks.

(26) The semiconductor device 50 can be a transistor that is formed of a plurality of (small) functional units 2 wired to each other which, in turn, can be transistors.

(27) The three functional units 2 are arranged side by side in a row on the second semiconductor wafer. The distance d.sub.5 between the functional units 2 is equal in each case.

(28) The distance d.sub.5 can be equal to the distance between the functional units 2 on the first semiconductor wafer (distance d.sub.3).

(29) The wiring comprises three conductor tracks: a gate conductor track 26, a source conductor track 27 and a drain conductor track 28.

(30) The gate conductor track 26 interconnects all gate contact areas 6 of the three functional units 2, the source conductor track 27 interconnects all source contact areas 7 and the drain conductor track 28 interconnects all drain contact areas 8.

(31) The second semiconductor wafer can comprise an integrated circuit, a processor and/or a die, onto which the functional units 2 can be (additionally) printed.

(32) The ends of the gate conductor track 26, source conductor track 27 and/or drain conductor track can be guided, for example, to an edge of the die in order to establish a connection from the die to the package or to be connected to other (semiconductor) devices.

(33) The conductor tracks can comprise metal, especially be made of metal.

(34) The conductor tracks can be made of a metallization plane or a plurality of metallization planes.

(35) The metallization plane can be applied to the second semiconductor wafer after the transfer of the functional units 2. After applying the metallization plane, the conductor tracks can be made of the metallization plane in further processing steps.

(36) The wiring can comprise applying and processing a plurality of (at least two) metallization planes.

(37) The conductor tracks can comprise aluminum or copper.

(38) The gate contact areas 6 and source contact areas 7 are at the same height (as seen in the x′ direction).

(39) The drain contact areas 8 are not at the same height as the other contact areas 6, 7.

(40) The gate conductor track 26 has a rectilinear path that is arranged beneath the gate contact areas 6 (as seen in the y′ direction), from which (rectangular) protruding regions 30 extend towards the gate contact areas 6 and contact the same.

(41) The source conductor track 27 has a rectilinear path that is arranged above the source contact areas 7 (as seen in the y′ direction), from which (rectangular) protruding regions 32 extend towards the source contact areas 7 and contact the source contact areas 7.

(42) The drain conductor track 28 can be of an exclusively rectilinear shape and is at the same height as the drain contact areas 8 or rather overlaps and contacts the same.

(43) FIG. 3 shows functional units 2 on a first semiconductor wafer that are identical to each other.

(44) The functional units can be unwired transistors (transistor precursors).

(45) The four functional units 2 are arranged in an array (grid).

(46) The functional units 2 on the first semiconductor wafer are arranged lying in a plane. The array/grid, in which the functional units 2 are arranged, is congruent with the plane spanned by a surface of the functional units 2.

(47) The coordinates can be clearly defined by an x-y coordinate system (or x′-y′ coordinate system on a second semiconductor wafer).

(48) The functional units 2 can be of a rectangular basic shape.

(49) The functional units 2 can be separated from each other by a trench 4.

(50) A distance d.sub.3 between the functional units 2 (as seen in the x direction) is equal in each case.

(51) Analogously, a distance d.sub.4 between the functional units 2 (as seen in the y direction) is equal as well.

(52) The distance d.sub.3 can be greater than the distance d.sub.4.

(53) The distances d.sub.3, d.sub.4 between the functional units (as seen in the x direction and the y direction, respectively) can be equal in size.

(54) A functional unit 2 comprises a plurality of active regions formed as elongate (finger-like regions.

(55) The functional unit 2 comprises a plurality of gate fingers 16, source fingers 17 and drain fingers 18. In this example, four gate fingers 16, three source fingers 17 and two drain fingers 18 are shown.

(56) The gate, source and drain fingers 16, 17, 18 are oriented vertically (along the y direction) and a width w thereof is less than a height h of the functional unit 2 (w<h), in particular, the width w can be 95% of the height h of the functional unit (or the width w is 5% less than the height h).

(57) The lengths l.sub.G, l.sub.S, l.sub.D of the gate fingers 16, the source fingers 17 and the drain fingers 18 differ (from each other).

(58) The lengths l.sub.G, l.sub.S, l.sub.D can be equal to each other.

(59) The distance d.sub.1 is the distance between a drain finger 18 and a gate finger 16.

(60) The distance d.sub.2 is the distance between a gate finger 16 and a source finger 17.

(61) The distance d.sub.1 is greater than the distance d.sub.2.

(62) The distance d.sub.1 can be equal to d.sub.2.

(63) The distance d.sub.1 between the drain finger 18 and the adjacent gate finger(s) 16 is equal in each case. The distance d.sub.2 between the gate fingers 16 and the source fingers 17 arranged adjacent thereto is equal as well. The distance d.sub.1 can differ from the distance d.sub.2.

(64) A first detailed view (on the left) in FIG. 3 shows a gate finger 16 and a source finger 17 of a functional unit 2 in an enlarged view.

(65) The gate finger 16 comprises a gate contact area 6 and the source finger 17 comprises a source contact area 7. The contact areas can be of a square basic shape.

(66) The contact areas 6, 7, 8 can be of a different basic shape.

(67) The gate contact area 6 and the source contact area 7 are not at the same height as seen in a y direction or are spaced from each other (distance d.sub.6) in the y direction.

(68) Each gate finger 16 and each source finger 17 can comprise at least one contact area 6, 7.

(69) The gate contact areas 6 can all be at a same height (same y coordinates). Analogously, the source contact areas 7 can all be at a same height or can be interconnected by a straight line in an x direction.

(70) A second detailed view (on the right) shows an enlarged section of a drain finger 18 of the functional unit 2. The drain finger 18 comprises a drain contact area 8.

(71) The drain contact area 8 can be of a square basic shape and can be arranged centrally (in the x direction) on the drain finger. Each of the gate contact area 6 and the source contact area 7 can also be arranged centrally on the drain finger 16 and source finger 17, respectively, as seen in the x direction.

(72) Each drain finger 18 can comprise at least one drain contact area 8.

(73) When each of the drain fingers 18 has a drain contact area 8, the drain contact areas 8 can all be arranged at a same height (same y coordinates) so that the drain contact areas 8 can be interconnected by a straight line in an x direction. The same applies to each of the gate fingers 16 and source fingers 17 that comprise a contact area.

(74) The contact areas 6, 7, 8 are arranged such that an imaginary straight line can be laid (drawn) in the x direction in each case, i.e. laid such that all contacts can be interconnected according to the terminal type (gate, drain, source), without the imaginary straight lines intersecting any contact of another terminal type, i.e. they are parallel to each other.

(75) A gate finger 16 can comprise at least two gate contact areas 6. The at least two gate contact areas 6 can be spaced from each other, especially be arranged at different heights in a y direction (having the same x coordinates).

(76) The at least two gate contacts 6 can be spaced from each other as well as from the contacts of the other terminal types 7, 8, in particular, they can be arranged in such a manner that imaginary straight lines, each intersecting only contacts of one terminal type, can be drawn in x directions of the functional unit 2 (having different y coordinates).

(77) The same principle can be applied to source fingers 17 and drain fingers 18 within the functional unit 2, each having at least two contact areas 7, 8.

(78) The gate contact areas 6, source contact areas 7 and drain contact areas 8 are not wired to each other within a functional unit 2 on the first semiconductor wafer.

(79) FIG. 4 shows a semiconductor device 50 on a second semiconductor wafer. The semiconductor device comprises two functional units 2 wired to each other on the second semiconductor wafer.

(80) The wiring comprises a plurality of conductor tracks: a gate conductor track 26, a source conductor track 27 and a drain conductor track 28. The conductor tracks 26, 27, 28 are rectilinear.

(81) The gate conductor track 26 interconnects all gate contact areas 6, the source conductor track 27 interconnects all source contact areas 7 and the drain conductor track 28 interconnects all drain contact areas 8 (not shown).

(82) This is illustrated in a first (on the left) and a second (on the right) detailed view of FIG. 4, in which each of the gate contact area 6, source contact area 7 and drain contact area 8 is shown overlapped by the gate conductor track 26, source conductor track 27 and drain conductor track 28.

(83) The functional units 2 are arranged side by side in a row and spaced from each other.

(84) The distance d.sub.5 is the distance between the functional units.

(85) The distance d.sub.5 can correspond to the distance d.sub.3 between the functional units 2 on the first semiconductor wafer.

(86) More than two wired functional units 2 can also be arranged on the second semiconductor wafer, in particular, at least five functional units 2 can be arranged side by side and wired to each other.

(87) Two rows of functional units 2 that are each arranged side by side and wired to each other can also be arranged on the second semiconductor wafer. In this case, the conductor tracks can also all be parallel to each other and interconnect only contacts of one terminal type in each case.

(88) It should be understood that the foregoing description is only illustrative of the present invention. Various alternatives and modifications can be devised by those skilled in the art without departing from the present invention. Accordingly, the present invention is intended to embrace all such alternatives, modifications, and variances that fall within the scope of the appended claims. The reference numerals recited in the claims are not intended to be read as limiting any terms or the scope of the claims.