METHOD FOR PRODUCING A SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE

Abstract

In at least one embodiment, the method is for producing a semiconductor device (1) and comprises the following steps in the stated order: A) providing a semiconductor body (2) having a top side (20), the semiconductor body (2) is based on SiC, B) producing a first layer (21) of the semiconductor body (2) next to the top side (20) by doping with a dopant (4), C) applying a carbon-containing layer (3) on the top side (20), D) implanting C into the first layer (21) through the carbon-containing layer (3), and E) performing a temperature treatment of the semiconductor body (2) when the carbon-containing layer (3) is still present on the top side (20).

Claims

1. A method for producing a semiconductor device comprising the following steps in the stated order: A) providing a semiconductor body having a top side, the semiconductor body is based on SiC, B) producing a first layer of the semiconductor body next to the top side by doping with a dopant, C) applying a carbon-containing layer on the top side, D) implanting C into the first layer through the carbon-containing layer with a dose of at most 110.sup.12 cm.sup.2, and E) performing a temperature treatment of the semiconductor body when the carbon-containing layer is still present on the top side, wherein a concentration of the dopant provided in step B) and being activated is at least three times and at most thirty times a concentration of C implanted in step D).

2. The method according to claim 1, wherein the concentration of the dopant provided in step B) and being activated is at least six times and at most fifteen times the concentration of C implanted in step D).

3. The method according to claim 1, wherein in step E) the temperature treatment includes applying a first temperature, wherein the first temperature is between 1400 C. and 1800 C. inclusive, wherein in step E) C diffuses from the carbon-containing layer into the first layer.

4. The method according to claim 1, further comprising a step B2) between steps B) and D): B2) activating the dopant by applying a second temperature, wherein the second temperature is between 1400 C. and 1800 C. inclusive.

5. The method according to claim 1, wherein in step E) C diffuses from the carbon-containing layer into the first layer and the dopant is activated, wherein in step E) the temperature treatment includes applying a third temperature, wherein the third temperature is between 1400 C. and 1800 C. inclusive, and wherein between steps A) and E) a temperature of the semiconductor body is kept below 800 C.

6. The method according to claim 1, wherein in step B) the doping is provided by means of ion implantation.

7. The method according to claim 1, wherein the dopant is Al, wherein the dopant is provided with a dose between 10.sup.13 cm.sup.2 and 10.sup.16 cm.sup.2.

8. The method according to claim 1, wherein in step D) a first implantation energy is at least 10 keV and is at most 300 keV.

9. The method according to claim 1, wherein after step D) a first box profile depth of the dopant is larger than a second box profile depth of C, wherein the first box profile depth is between 0.1 m and 1.2 m inclusive.

10. The method according to claim 1, further comprising a step B1) between steps B) and C): B1) etching the semiconductor body so that a mesa is formed, an etching depth is larger than a thickness of the first layer.

11. The method according to claim 1, wherein in step C) the carbon-containing layer is applied all over the semiconductor body, wherein the carbon-containing layer comprises at least one of graphite and a photoresist, and a thickness of the carbon-containing layer is at least 0.1 m and at most 0.9 m.

12. The method according to claim 1, wherein in the finished semiconductor device the semiconductor body further comprises a second layer directly on a side of the first layer remote from the top side, wherein the second layer is doped with a lower doping concentration than the first layer, wherein a thickness of the second layer is between 10 m and 100 m.

13. The method according to claim 1, wherein the first layer is of 4H-SiC, and wherein in the finished semiconductor device the first layer is an anode layer.

14. The method according claim 1, wherein the finished semiconductor device is a pin diode or is an insulated-gate bipolar transistor, IGBT, or a reverse-conducting insulated-gate bipolar transistor, RC-IGBT.

15. (canceled)

Description

[0057] In the figures:

[0058] FIGS. 1 and 2 are schematic block diagrams of exemplary embodiments of methods for manufacturing semiconductor devices described herein,

[0059] FIG. 3 is a schematic representation of doping profiles provided by methods described herein,

[0060] FIGS. 4 to 9 are schematic sectional views of method steps of an exemplary embodiment of a method for manufacturing semiconductor devices described herein,

[0061] FIGS. 10 to 12 are schematic sectional views of exemplary embodiments of semiconductor devices described herein, and

[0062] FIG. 13 is a representation of deep level transient spectroscopy data of an exemplary embodiment of a semiconductor device described herein and of a comparative example.

[0063] FIGS. 1 and 2 are schematic representations of methods to produce semiconductor devices 1. In a method step S1, a semiconductor body 2 is provided, see also the description on FIGS. 4 to 9 below. For example, the semiconductor body is of SiC.

[0064] Subsequently, in method step S2, a first layer 21 of the semiconductor body 2 is produced by doping a respective region of the semiconductor body 2 with a dopant 4. For example, the first layer 21 is p-doped in step S2. This can be achieved, for example, by ion implantation with the dopant 4. The dopant 4 is, for example, Al.

[0065] Then, in step S3, a carbon-containing layer 3 is applied on a top side 20 of the semiconductor body 2. The top side 20 can be formed partially or completely by the first layer 21.

[0066] In a subsequent step S4 C is implanted into the first layer with a lower concentration than the dopant 4.

[0067] According to FIG. 1, in step S5 a temperature treatment is performed at a third temperature. In this step, both the dopant is activated and C can diffuse from the carbon-containing layer 3 into the semiconductor body 2, for example, into and/or through the first layer 21. Hence, in the method of FIG. 1 in the relevant method steps there is only one temperature treatment of the semiconductor body 2 at an elevated temperature of, for example, above 1000 C.

[0068] Contrary to that, in FIG. 2 it is illustrated that there is step S31. In step S31, a temperature treatment at a second temperature is performed. During this temperature treatment, the dopant 4 is activated. Then, after step S4, there is also step S5, but in this step S5 diffusion of C occurs at a first temperature. Hence, in the method of FIG. 2 the activation and the diffusion can be performed separated from each other. It is possible that the first temperature is lower than the second temperature.

[0069] In FIG. 3, resulting doping profiles of the dopant 4, like Al, and of the implanted C are illustrated. Both profiles are box profiles. It is noted that in FIG. 3 the implanted concentration c of the dopant 4 and not a concentration of activated dopant 4 is shown. The concentration of the activated dopant 4 is about two order of magnitude lower than the actually implanted concentration c of the dopant 4. Thus, a maximum implanted concentration c of the dopant 4 is about three order of magnitude higher than a maximum implanted concentration c of C.

[0070] As can also be seen from FIG. 3, the box profile of the dopant 4 has a depth T of about 0.3 m to 0.4 m. A depth T of the box profile of the implanted C is about 0.2 m. Next to the top side 20, the doping concentration c is in both cases relatively low, compared with the maximum implanted concentrations.

[0071] For example, the methods of FIGS. 1 and 2 may be performed as follows:

[0072] First, the anode, that is, the first layer 21, is formed by Al ion implantation. For instance, Al implantation energies of 30 keV, 60 keV, 110 keV and 180 keV and a total dose of 10.sup.15 cm.sup.2, performed at temperatures of at least 100 C., will lead to an Al concentration, [Al], plateau of about 10.sup.20 cm.sup.3 and to a box profile depth of about 0.4 m. After this, Al activation is carried out at a temperature of 1700 C. for 30 min.

[0073] Then, C implantation is performed in the p.sup.+ area, that is, part of the first layer 21, through the previously applied C-cap, that is, the carbon-containing layer 3, which has a thickness of, for example, about 0.15 m. C implantation energies should be chosen so that the C-implant profile is within 0.1 m from the Al box profile tail region located at T0.4 m. The implant C dose should be chosen so that the implanted C.sub.i concentration is lower than the implanted [Al], after activation. By assuming an activation ratio of 2% of the dopant 4, the implanted [C.sub.i] is, for example, at most 10.sup.17 cm.sup.3, corresponding to [Al]/[C.sub.i]>10. For example, for the profile of FIG. 3, C has been implanted at 80 keV and with a dose of 510.sup.9 cm.sup.2.

[0074] At last, annealing at at most 1600 C. is carried out to diffuse the C.sub.i. C.sub.i, coming from the C-cap, will also be injected in a second layer of the semiconductor body 2, like a drift layer. Since their concentration is not sufficient to decrease [Z.sub.1/2] to below a detection limit, which is, for example, around 10.sup.10 cm.sup.3, the implanted C.sub.i will top them up.

[0075] Alternatively, see FIG. 2, C implantation can be performed before Al activation. In this case, the activation temperature also allow C.sub.i diffusion.

[0076] Longer annealing times of, for example, at least 30 min, can be chosen so to diffuse C.sub.i in thicker second layers 22 having a thickness of about 100 m.

[0077] As a result, the [V.sub.c] will decrease to below the detection limit. Two other levels may be detected, called ON1 and ON2, compare B. Zippelius et al. as cited above. These levels have no impact on device performance. It is noted that, for example, in a standard p.sup.+in diode, a certain amount of V.sub.c is always detected, due to p.sup.+ activation.

[0078] For example, by means of deep-level transient spectroscopy, DLTS, the presence of V.sub.c (Z.sub.1/2) can be demonstrated in a p.sup.+n diode not treated as described herein, and also the absence of V.sub.c in a p.sup.+n diode treated with the described method and appearance of ON1 and ON2 can be demonstrated.

[0079] In FIGS. 4 to 9, an example for producing a semiconductor device 1 which is a pin diode is illustrated. According to FIG. 4, the semiconductor body 2 is provided. The semiconductor body 2 includes a third layer 23 on a second layer 22. The second layer 22 is, for example, intrinsically doped or only very weakly n-doped. The third layer 23 is, for example, n-doped. The top side 20 is at the second layer 22. The third layer 23 and/or the second layer 22 may be provided by means of epitaxy.

[0080] In FIG. 5 it is shown that the first layer 21 is formed by doping the semiconductor body 2 next to the top side 20 with the dopant 4 which is, for example, Al. A thickness of the first layer 21 is, for example, about 0.4 m.

[0081] After that, a mesa 5 is formed by etching, see FIG. 6. The etching terminates in the second layer 22 so that the first layer 21 is completely removed in places.

[0082] According to FIG. 7, another implantation with, for example, also of Al, is carried out for field protection, or to create a junction termination extension, JTE, as a fourth layer 24 of the semiconductor body. Moreover, the carbon-containing layer 3 is applied all over the top side 20, that is, at the mesa 5 and also at the second layer 22 and the fourth layer 24. The fourth layer 24 may not extend completely across the second layer 22 but may terminate in a lateral direction nearby the mesa 5. Otherwise, for the fourth layer 24 the same may apply as for the first layer 21.

[0083] The implanted area is activated at 1700 C., for example, and C is implanted afterwards through the carbon-containing layer 3, see FIG. 8. The carbon-containing layer 3 may be a continuous, hole-free and, thus, uninterrupted layer. For example, the carbon-containing layer 3 is of constant thickness.

[0084] In FIG. 8 it is also illustrated that the first layer 21 may optionally be composed of two regions, in FIG. 8 schematically separated from one another by a horizontal line within the first layer 21. In the upper region next to the top side 20, there can be a higher maximum p-doping concentration than in the lower region. Hence, the upper region may be p.sup.+-doped and may serve as a contact layer, while the lower region can be p-doped. This can apply for all other examples of the semiconductor device 1 as well.

[0085] After this, see FIG. 9, a low temperature annealing is performed, for example, at a temperature below 1600 C., in order to diffuse C.sub.i. This will result in a V.sub.c poor second layer 22 which is, for example, a drift layer.

[0086] After temperature treatment and before application of, for example, electrodes or electrically insulating layers, the carbon-containing layer 3 can completely be removed.

[0087] An example of the finished semiconductor device 1 is shown in FIG. 10. The semiconductor device 1 is a Sic-p.sup.+in diode comprising the mesa 5. In the mesa 5, there can be a fifth layer 25 of the semiconductor body 2 which is, for example, a p.sup.+ contact layer. Further, the first layer 21 is in the mesa 5. Starting from the first layer 21, the fourth layer 24 can extend laterally next to the mesa 5 so that the JTE is formed. The layers 24, 25 can be regarded as being special parts of the first layer 21, or may be regarded as being separate layers.

[0088] Below the mesa 5, there is the second layer 22 which is, for example, slightly n.sup.-doped with a concentration of, for example, about 110.sup.15 cm.sup.3 and may have a thickness of about 70 m. The third layer 23 is, for example, an n.sup.+-doped substrate made of SiC and with a doping concentration of about 510.sup.18 cm.sup.3. A thickness of the third layer 23 is, for example, about 0.25 mm. Lateral sides of the mesa and the exposed regions of the second and fourth layers 22, 24 are coved with an electrically insulating layer 6 which is, for example, of silicon dioxide.

[0089] At the fifth layer 25, atop the mesa 5, there is a first electrode 71, like an anode, and at the third layer 23 there is a second electrode 72, like a cathode. As an option, there can be a circumferential sixth layer 26 of the semiconductor body 2 which is, for example, n.sup.+-doped and which serves as a channel stop. Seen in top view, the mesa 5 can be surrounded all around by the fourth layer 24 and the sixth layer 26, for example, in a rotational symmetric manner.

[0090] Otherwise, the same as to FIGS. 1 to 9 may also apply to FIG. 10, and vice versa.

[0091] The semiconductor device 1 of FIG. 11 is also a pin diode based on 4H-SiC, but contrary to the semiconductor device 1 of FIG. 10 is of planar fashion so that there is the plane top side 20 without any mesa. In the design of FIG. 11, the first electrode 71 is located at a lateral edge of the device 1. The first layer 21 is of well-shape and is located in the second layer 22. A thickness of the second layer 22 is, for example, about 10 m. For example, the second layer 22 and the third layer 23 are n-doped with concentrations of about 910.sup.15 cm.sup.3 and 110.sup.19 cm.sup.3, respectively.

[0092] Otherwise, the same as to FIGS. 1 to 10 may also apply to FIG. 11, and vice versa.

[0093] In FIG. 12 it is shown that the semiconductor device 1 is an insulated insulated-gate bipolar transistor, IGBT. Thus, the first layer 21 is a well region. In the well region, there is the fifth layer which is, for example, a p.sup.+ plug at the first electrode 71 which is, for example, an emitter electrode. Further, in the well region there is a seventh layer of the semiconductor body 2 configured as an emitter region. The second layer 22 is thus an n.sup. drift region. For example, the second layer 22 is a substrate with a thickness between 50 m and 200 m. A doping concentration of the drift layer is, for example, about 210.sup.14 cm.sup.3.

[0094] The second layer 22 extends until the top side 20, between two well regions, seen in cross-section. At the top side 20, atop the well regions and said central part of the second layer 22, there is the insulation layer 6 which separates a third electrode 73 from the semiconductor body 2. The third electrode 73 is a gate electrode.

[0095] As an option, below the second layer 22 there is an eight layer 28 of the semiconductor body 2 which can be a buffer layer. For example, the buffer layer is n-doped with a maximum doping concentration of about 110.sup.18 cm.sup.3. A thickness of the buffer layer may be between 2 m and 10 m inclusive.

[0096] The third layer 23 is located at a side of the second layer 22 remote from the top side 20 or at a side of the eighth layer 28 remote from the top side 20. The third layer 23 is a collector region. The third layer 23 has, for example, a doping concentration of about 110.sup.19 cm.sup.3. A thickness of the third layer 23 is, for example, between 2 m and 10 m inclusive. The second electrode 72 at the third layer 23 is a collector electrode.

[0097] Analogously, the semiconductor device 1 can be a metal-insulator-semiconductor field-effect transistor, MISFET, or a metal-oxide-semiconductor field-effect transistor, MOSFET. In this case, the eighth layer 28 may be omitted, and the third layer 23 is an n-doped drain region having, for example, a maximum doping concentration of at least 110.sup.18 cm.sup.3 or at least 510.sup.18 cm.sup.3 or at least 110.sup.19 cm.sup.3 and/or of at most 510.sup.20 cm.sup.3 or at most 210.sup.20 cm.sup.3 or at most 110.sup.20 cm.sup.3. In this case, the seventh layer 27 is a source region and the first and second electrodes 71, 72 are a source electrode and a drain electrode, respectively.

[0098] Other than shown, the IGBT or MISFET or MOSFET does not need to be of planar design, but can also be of trench design with the gate electrode 73 accommodated in a trench, not shown.

[0099] Otherwise, the same as to FIGS. 1 to 11 may also apply to FIG. 12, and vice versa.

[0100] The data in FIG. 13 of a comparative example 9 and of a semiconductor device 1 described herein was obtained by Deep Level Transient Spectroscopy, DLTS. The measurements were done with a reverse bias V.sub.r of 5 V and a pulse voltage V.sub.p of 5 V. A filling pulse length was 1 ms at a period width of 0.2 s. The semiconductor device 1 was treated as described in connection with FIGS. 4 to 9 while in case of the comparative example 9 there was not low-dose C ion implantation through a carbon-containing layer. It can be seen that in the comparative example 9 there is a strong presence of V.sub.c as indicated by the Z.sub.1/2 peak. Contrary to that, in the exemplary semiconductor device 1 there is no Z.sub.1/2 peak, but instead peaks associated with the states ON1, ON2 appear.

[0101] Typically, the V.sub.c concentration in as grown n-type 4H-SiC is between 10.sup.11 cm.sup.3 and 10.sup.12 cm.sup.3. With such concentrations, the minority carrier lifetime is around 1 s. This value is rather low and not suitable for SiC bipolar devices. An acceptable [V.sub.c] is, for example, lower than 10.sup.11 cm.sup.3. Since High Voltage SiC bipolar devices rely on regions with low doping concentration, that is, for example, 10.sup.14 cm.sup.3, the threshold for detection of [V.sub.c] may be around 10.sup.10 cm.sup.3. Hence, that the threshold limit for V.sub.c detection is about four orders of magnitude lower than the doping concentration. Thus, a SiC bipolar device with a doping concentration of 10.sup.14 cm.sup.3 and a [V.sub.c] of 510.sup.10 cm.sup.3 to 810.sup.10 cm.sup.3 or even lower would work fine.

[0102] The method described herein goes ahead with the following benefits, for example: [0103] Performing C implantation in the anode through the C-cap allows effective V.sub.c removal, because C.sub.i are supplied by the C-cap and by the implanted C. [0104] Unlike in Hamada et al., C implantation can be done at low doses, thus avoiding amorphization in the drift layer. [0105] Also unlike in Hamada et al., C implantation is done in the anode and not in the drift layer, thus avoiding doping compensation, because C.sub.i are acceptors in n-type Sic. [0106] Unlike in Storasta et al., no structuring, like etching, of the C-containing layer is needed. [0107] Unlike in Ayedh et al., no residual V.sub.c are left, because C.sub.i are provided not only by the C-cap but also from the implantation step. [0108] The C low dose implantation avoids excessive formation of defects in the anode layer, that is, the first layer, thus preserving the injection efficiency. [0109] 7) Reverse engineering is possible in the final product, for example, by secondary-ion mass spectrometry, SIMS, in order to detect C in the anode layer. [0110] Reverse engineering is possible in the final product also, for example, by DLTS, in order to detect ON1 and ON2 states. [0111] Anode layers of any thickness are possible to be formed.

[0112] The components shown in the figures follow, unless indicated otherwise, exemplarily in the specified sequence directly one on top of the other. Components which are not in contact in the figures are exemplarily spaced apart from one another. If lines are drawn parallel to one another, the corresponding surfaces may be oriented in parallel with one another. Likewise, unless indicated otherwise, the positions of the drawn components relative to one another are correctly reproduced in the figures.

[0113] The invention described here is not restricted by the description on the basis of the exemplary embodiments. Rather, the invention encompasses any new feature and also any combination of features, which includes in particular any combination of features in the patent claims, even if this feature or this combination itself is not explicitly specified in the patent claims or exemplary embodiments.

LIST OF REFERENCE SIGNS

[0114] 1 semiconductor device [0115] 2 semiconductor body [0116] 20 top side of the semiconductor body [0117] 21 first layer of the semiconductor body [0118] 22 second layer of the semiconductor body [0119] 23 third layer of the semiconductor body [0120] 24 fourth layer of the semiconductor body [0121] 25 fifth layer of the semiconductor body [0122] 26 sixth layer of the semiconductor body [0123] 27 seventh layer of the semiconductor body [0124] 28 eighth layer of the semiconductor body [0125] 3 carbon-containing layer [0126] 4 dopant [0127] 5 mesa [0128] 6 insulation layer [0129] 71 first electrode [0130] 72 second electrode [0131] 9 comparative example [0132] A absolute temperature in K [0133] Al aluminum ion implantation [0134] C concentration in cm.sup.3 [0135] C carbon ion implantation [0136] DLTS deep level transient spectroscopy data in pF [0137] ON1 first other level in the band structure [0138] ON2 second other level in the band structure [0139] S . . . method step [0140] T depth from the top side into the semiconductor body [0141] Z.sub.1/2 active level in the bandgap