An interface circuit, comprising: a signal line having signal, auxiliary and connection nodes defined therealong, the connection node for connection to a transmission line; signal-handling circuitry connected to the signal line at the signal node; an auxiliary circuit connected to the signal line at the auxiliary node; a signal pair of inductors connected in series along the signal line adjacent to and either side of the signal node; and an auxiliary pair of inductors connected in series along the signal line adjacent to and either side of the auxiliary node, wherein: the signal pair of inductors are configured to have a mutual coupling defined by a coupling coefficient kS; the auxillary pair of inductors are configured to have a mutual coupling defined by a coupling coefficient kA; and kS has a positive value and kA has a negative value.

An interface circuit, comprising: a signal line having signal, auxiliary and connection nodes defined therealong, the connection node for connection to a transmission line; signal-handling circuitry connected to the signal line at the signal node; an auxiliary circuit connected to the signal line at the auxiliary node; a signal pair of inductors connected in series along the signal line adjacent to and either side of the signal node; and an auxiliary pair of inductors connected in series along the signal line adjacent to and either side of the auxiliary node, wherein: the signal pair of inductors are configured to have a mutual coupling defined by a coupling coefficient kS; the auxillary pair of inductors are configured to have a mutual coupling defined by a coupling coefficient kA; and kS has a positive value and kA has a negative value.

A circuit is disclosed. The circuit includes an input port, an output port, a squelch detector and a disconnect detector. The squelch detector and the disconnect detector are enabled or disabled by a signal such that only one of the squelch detector and the disconnect detector is active at a given time. When the squelch detector is active, a threshold generator generates a squelch threshold for the squelch detector based on a squelch configuration data indicative of a predefined squelch threshold. When the disconnect detector is active, the threshold generator generates a disconnect threshold for the disconnect detector based on a disconnect configuration data indicative of a predefined disconnect threshold.

An integrated isolator circuit for isolating receiver and transmitter in a Time-Division Duplex transceiver is disclosed. The integrated isolator circuit comprises a first node, a second node and. a third node. The integrated isolator circuit further comprises a first capacitor connected in series with a first switch and connected between the first and second nodes. The integrated isolator circuit further comprises a first inductor connected between the first and second nodes and a second capacitor connected between the second node and the third node. The first switch has an on state and an off state, and the integrated isolator circuit is configured to have a different impedance at a certain operating frequency by controlling the state of the first switch.

An antenna device is provided that can be designed easily and includes a flat antenna of which communication characteristics do not change significantly even when there exist metallic objects or the like in the surroundings. Moreover, the flat antenna is provided with an antenna-side signal line path conductor, an antenna-side first ground conductor, a matching circuit part, and an antenna-side connector part which are provided in an antenna-side insulator. The antenna device further includes a signal transmission cable that is provided with a radiation area setting part in the vicinity of a cable-side connector part. The antenna device is designed such that, by connecting the antenna-side connector part and the cable-side connector part to each other, substantially the entire surface of the flat antenna serves as a radiation part that radiates electromagnetic waves.

A method of designing a microwave filter using a computerized filter optimizer, comprises generating a filter circuit design in process (DIP) comprising a plurality of circuit elements having a plurality of resonant elements and one or more non-resonant elements, optimizing the DIP by inputting the DIP into the computerized filter optimizer, determining that one of the plurality of circuit elements in the DIP is insignificant, removing the one insignificant circuit element from the DIP, deriving a final filter circuit design from the DIP, and manufacturing the microwave filter based on the final filter circuit design.

A method of designing a microwave filter using a computerized filter optimizer, comprises generating a filter circuit design in process (DIP) comprising a plurality of circuit elements having a plurality of resonant elements and one or more non-resonant elements, optimizing the DIP by inputting the DIP into the computerized filter optimizer, determining that one of the plurality of circuit elements in the DIP is insignificant, removing the one insignificant circuit element from the DIP, deriving a final filter circuit design from the DIP, and manufacturing the microwave filter based on the final filter circuit design.

A noise filter includes a filter circuit including a noise reduction element that reduces a noise component, a conductive first circuit connection member to which a first connection portion of the noise reduction element is electrically connected, and a conductive second circuit connection member to which a second connection portion of the noise reduction element is electrically connected, a first electric connection structure that electrically connects an intermediate connection portion of a core wire of a first electric wire to the first circuit connection member, and a second electric connection structure that electrically connects an intermediate connection portion of a core wire of a second electric wire whose one end is grounded, to the second circuit connection member.

An impedance adjustment device includes a variable capacitor unit. A microcomputer changes the capacitance value of the variable capacitor unit by switching PIN diodes included in n capacitor circuits on or off separately. Thus, the impedance on the plasma generator side when viewed from a high frequency power supply is adjusted. When changing the capacitance value of the variable capacitor unit to a target capacitance value, the microcomputer changes the capacitance value. When a predetermined period passes after the change of the capacitance value, the microcomputer changes the capacitance value again.

The present disclosure may include, for example, a tunable capacitor having a decoder for generating a plurality of control signals, and an array of tunable switched capacitors comprising a plurality of fixed capacitors coupled to a plurality of switches. The plurality of switches can be controlled by the plurality of control signals to manage a tunable range of reactance of the array of tunable switched capacitors. Additionally, the array of tunable switched capacitors is adapted to have non-uniform quality (Q) factors. Additional embodiments are disclosed.