In one aspect there is provided a method. The method may include collecting one or more functions that implement the decision logic of a solution. A snapshot of the one or more functions can be generated. The snapshot can executable code associated with the one or more functions. The solution can be deployed by at least storing the snapshot of the one or more functions to a repository Systems and articles of manufacture, including computer program products, are also provided.

A memory device includes a plurality of data input pads and at least one test data input pad. The memory device also includes a plurality of data input circuits corresponding to a plurality of channels, respectively, the plurality of data input circuits suitable for transmitting respective data received through the data input pads to the corresponding channels. The memory device further includes a test control circuit suitable for selecting at least one data input circuit among the plurality of data input circuits based on test mode information and suitable for controlling the selected data input circuit to transmit set data to the corresponding channel, during a test operation.

A memory device includes a plurality of data input pads and at least one test data input pad. The memory device also includes a plurality of data input circuits corresponding to a plurality of channels, respectively, the plurality of data input circuits suitable for transmitting respective data received through the data input pads to the corresponding channels. The memory device further includes a test control circuit suitable for selecting at least one data input circuit among the plurality of data input circuits based on test mode information and suitable for controlling the selected data input circuit to transmit set data to the corresponding channel, during a test operation.

A solid state drive having a drive aggregator and a plurality of component solid state drive, including a first component solid state drive and a second component solid state drive. The drive aggregator has at least one host interface, and a plurality of drive interfaces connected to the plurality of component solid state drives. The drive aggregator is configured to generate, in the second solid state drive, a copy of a dataset that is stored in the first component solid state drive. In response to a failure of the first component solid state drive, the drive aggregator is configured to substitute a function of the first component solid state drive with respect to the dataset with a corresponding function of the second component solid state drive, based on the copy of the dataset generated in the second component solid state drive.

Numerous examples of a precision programming apparatus are disclosed for precisely and quickly depositing the correct amount of charge on the floating gate of a non-volatile memory cell within a vector-by-matrix multiplication (VMM) array in an artificial neural network. In one example, a neuron output circuit for providing a current to program as a weight value in a selected memory cell in a vector-by-matrix multiplication array is disclosed, the neuron output circuit comprising a first adjustable current source to generate a scaled current in response to a neuron current to implement a positive weight, and a second adjustable current source to generate a scaled current in response to a neuron current to implement a negative weight.

System and method for providing fault tolerance in virtualized computer systems use a first guest and a second guest running on virtualization software to produce outputs, which are produced when a workload is executed on the first and second guests. An output of the second guest is compared with an output of the first guest to determine if there is an output match. If there is no output match, the first guest is paused and a resynchronization of the second guest is executed to restore a checkpointed state of the first guest on the second guest. After the resynchronization of the second guest, the paused first guest is caused to resume operation.

A data processing apparatus (2) has scalar processing circuitry (32-42) and vector processing circuitry (38, 40, 42). When executing main scalar processing on the scalar processing circuitry (32-42), or main vector processing using a subset of said plurality of lanes on the vector processing circuitry (38, 40, 42), checker processing is executed using at least one lane of the plurality of lanes on the vector processing circuitry (38, 40, 42), the checker processing comprising operations corresponding to at least part of the main scalar/vector processing. Errors can then be detected based on a comparison of an outcome of the main processing and an outcome of the checker processing. This provides a technique for achieving functional safety in a high end processor with better performance and reduced hardware cost compared to a dual/triple core lockstep approach.

Staging data on a storage element integrating fast durable storage and bulk durable storage, including: receiving, at a storage element integrating fast durable storage and bulk durable storage, a data storage operation from a host computer; storing data corresponding to the data storage operation within fast durable storage in accordance with a first data resiliency technique; and responsive to detecting a condition for transferring data between fast durable storage and bulk durable storage, transferring the data from fast durable storage to bulk durable storage in accordance with a second data resiliency technique.

Techniques provide for data synchronization. For example, such a technique may involve: obtaining respective synchronization characteristics of a group of synchronization jobs to be processed, each synchronization characteristic indicating at least one of an expected completion time instant and an amount of data to be synchronized of a corresponding synchronization job; prioritizing the group of the synchronization jobs based on the synchronization characteristics; and controlling execution of the group of the synchronization jobs based on a result of the prioritizing. Accordingly, high priority is given to the synchronization jobs which can be rapidly completed thereby improving the Recovery Point Objective (RPO) achievement rate before occurrence of a failure.

A method for targeted repair of a hardware component in a computing device that is part of a cloud computing system includes monitoring a plurality of hardware components in the computing device. At some point, a defective sub-component within the hardware component of the computing device is identified. In addition to the defective sub-component, the hardware component also includes at least one sub-component that is functioning properly and a spare component that can be used in place of the defective sub-component. The method also includes initiating a targeted repair action while the computing device is connected to the cloud computing system. The targeted repair action prevents the defective sub-component from being used by the computing device without preventing sub-components that are functioning properly from being used by the computing device. The targeted repair action causes the spare component to be used in place of the defective sub-component.