A method and/or system for checking the bus/interface between a host and a memory system during memory access operations includes a memory system having one or more of the data memory devices and a spare memory device; providing a bus/interface between a host and the memory system; selecting information on a per memory device basis to associate with a spare memory device; disassociating the selected information from the one or more data memory devices and associating the selected information with the spare memory device; adding Cyclical Redundancy Check (CRC) code to the one or more data memory devices from which the selected information was disassociated; transferring the CRC code and information over the bus and interface between the host and the memory system; and checking the bus interface with the CRC code added to the one or more data memory devices.

A noise estimation method includes decomposing a first matrix in which values of elements are represented by binary values into a coefficient matrix and a basic matrix, and estimating an element including noise among elements of the first matrix based on a result of comparison between a second matrix obtained by combining the coefficient matrix with the basic matrix and the first matrix.

The disclosure includes a computer-implemented method for providing fast data access after a drive failure, a computer program product, and a RAID controller. One embodiment may comprise identifying a RAID array, the RAID array comprising a plurality of storage volumes, identifying an unused block of a provisioned volume in the RAID array, and copying a redundant copy of high value host writes to the unused block. The copying may comprise, for primary strips in the RAID array, creating one or more secondary strips mirroring the primary strips such that each of pair of primary-secondary strips reside on different storage volumes from each other.

A secure computing platform and method for securely enabling inserted or replacement hardware devices during boot of a computing platform are discussed. More particularly, an authorized list holding identifying information associated with approved insertable or replaceable hardware devices is maintained in non-volatile storage and checked by the firmware during a platform boot sequence against identifying information provided by the inserted or replacement hardware devices. Only devices whose information matches the stored authorized list information are enabled.

In one aspect there is provided a method. The method may include collecting one or more functions that implement the decision logic of a solution. A snapshot of the one or more functions can be generated. The snapshot can executable code associated with the one or more functions. The solution can be deployed by at least storing the snapshot of the one or more functions to a repository Systems and articles of manufacture, including computer program products, are also provided.

In one aspect there is provided a method. The method may include collecting one or more functions that implement the decision logic of a solution. A snapshot of the one or more functions can be generated. The snapshot can executable code associated with the one or more functions. The solution can be deployed by at least storing the snapshot of the one or more functions to a repository Systems and articles of manufacture, including computer program products, are also provided.

Systems and methods for performing data protection operations including replication management or data copy operations. Agent-less data protections are performed. A management server is configured to perform data operations on a production host without installing an agent on the production host. A driver is adapted to aid in performing the data protection operations and communications between the management server and the driver such as commands are achieved via a storage array.

In an on-vehicle control device, control units of multiple sections forming a redundant section include fail-safe calculation units that complement each other by respective calculation results. The control united in which the fail-safe calculation units are disposed are configured as a collective aggregate, the control units include calculation boards configured to perform calculation processing on the multiple sections, respectively, and output boards configured to output calculation results of the calculation processing by the calculation boards, and a common unit including a common interface connected to a plurality of the output boards respectively corresponding to the multiple sections is aggregated in a partial specific region of the aggregate.

A device, comprising: a main module; a plurality of secondary modules; and a data bus configured to enable data transmission between the main module and the plurality of secondary modules over a data line of the data bus; wherein each of the plurality of secondary modules is configured with a unique secondary address used by the main module to communicate with the respective secondary module over the data line, wherein the main module is operable to configure a first two or more of the plurality of secondary modules with a first common secondary address for simultaneous data transmission from the main module to the first two or more of the plurality of secondary modules over the data line.

The present invention relates to a single-board processor card configured for use in a 1U CubeSat payload form-factor multi-purpose architecture, including: a field-programmable-gate-array (FPGA) which is reconfigurable in flight; wherein a configuration memory of the FPGA can be scrubbed in flight to correct errors or upsets; and a radiation-hardened monitor (RHM) which provides radiation mitigation and system monitoring of the single-board processor card, and which reconfigures said FPGA during flight, scrubs the configuration memory, and monitors a health of the FPGA. The 1U CubeSat payload form-factor multi-purpose architecture includes a backplane having a plurality of slots, one of the plurality of slots which accommodates the single-board processor card, wherein the backplane routes signals to a plurality of standard-sized processor cards, interchangeably disposed in any of the plurality of slots.