An electronic apparatus is provided. The electronic apparatus includes a storage storing error-related information of an external electronic apparatus, and a processor configured to obtain first error-related information with respect to a target time interval and second error-related information with respect to a standard time interval including the target time interval and time intervals other than the target time interval, from the storage, obtain frequency information for each number of error occurrences with respect to the target time interval based on the first error-related information and frequency information for each number of error occurrences with respect to the standard time interval based on the second error-related information, and compare the frequency information for each number of error occurrences with respect to the target time interval with the frequency information for each number of error occurrences with respect to the standard time interval to identify an error occurrence level with respect to the target time interval.

A memory system includes a memory device including a plurality of memory units capable of inputting or outputting data individually, and a controller coupled with the plurality of memory units via a plurality of data paths. The controller is configured to perform a correlation operation on two or more read requests among a plurality of read requests input from an external device, so that the plurality of memory units output plural pieces of data corresponding to the plurality of read requests via the plurality of data paths based on an interleaving manner. The controller is configured to determine whether to load map data associated with the plurality of read requests before a count of the plurality of read requests reaches a threshold, to divide the plurality of read request into two groups based on whether to load the map data, and to perform the correlation operation per group.

An information processing device and information processing method with improved error tolerance are implemented. There is included a data processing unit that executes lockstep processing in which a plurality of processing systems executes the same task and error verification is performed by comparing execution results. In a case where an error is detected in the lockstep processing, the data processing unit increases supply voltage to a CPU circuit system that executes the task, processing of lowering a supply clock, or the like, as control for improving noise tolerance of the CPU circuit system, and moreover, performs re-execution processing of the task by using more processing systems than the processing systems before the error detection.

The present disclosure relates to a method in a distributed and non-hierarchical node comprising a set of data items for determining a synchronization state between said node and one or more distributed and non-hierarchical nodes communicatively coupled to form a cluster, wherein the set of data items are locally replicated at each node. The method comprises generating a snapshot comprising information relating to the set of data items at a snapshot time T.sub.s, said information identifying changes to the data items where each change comprises a time stamp, where only changes to the data items with a time stamp<T.sub.0, where T.sub.s>T.sub.0, are included in the snapshot, although changes to the data items up to the time T.sub.s, have been received and stored in the nodes, receiving corresponding generated snapshots from all other nodes in the cluster, and determining a synchronization state based on a comparison between the generated and received snapshots. The synchronization state is determined to be not synchronized if the generated snapshot and the received corresponding snapshots do not all match.

An apparatus comprises a plurality of redundant processing units to perform data processing redundantly in lockstep; common mode fault detection circuitry to detect an event indicative of a potential common mode fault affecting each of the plurality of redundant processing units; a memory shared between the plurality of redundant processing units; and memory checking circuitry to perform a memory scanning operation to scan at least part of the memory for errors; in which the memory checking circuitry performs the memory scanning operation in response to a common mode fault signal generated by the common mode fault detection circuitry indicating that the event indicative of a potential common mode fault has been detected.

Concepts and technologies are disclosed herein for providing a network virtualization policy management system. An event relating to a service can be detected. A first policy that defines allocation of hardware resources to host the virtual network functions can be obtained, as can a second policy that defines deployment of the virtual network functions to the hardware resources. The hardware resources can be allocated based upon the first policy and the virtual network functions can be deployed to the hardware resources based upon the second policy.

A parallel processing system includes at least three parallel processors, state monitoring circuitry, and state reload circuitry. The state monitoring circuitry couples to the at least three parallel processors and is configured to monitor runtime states of the at least three parallel processors and identify a first processor of the at least three parallel processors having at least one runtime state error. The state reload circuitry couples to the at least three parallel processors and is configured to select a second processor of the at least three parallel processors for state reload, access a runtime state of the second processor, and load the runtime state of the second processor into the first processor. Monitoring and reload may be performed only on sub-systems of the at least three parallel processors. During reload, clocks and supply voltages of the processors may be altered. The state reload may relate to sub-systems.

An embodiment method is disclosed for deriving an estimation value of a clock-error for a slave clock, wherein the slave clock is set at a nominal slave period and outputs a sequence of slave clock signals at an actual slave period, and wherein a difference between the actual slave period and the nominal slave period is approximated by the estimation value of the clock-error.

A self-healing data synchronization process includes an initial stage in which a collection of data change events is received, a set of data record(s) corresponding to the data change event(s) is identified, and a syncing of the set of data record(s) is initiated. Data that indicates which data record(s) successfully synced and which failed is stored. During a subsequent stage of the self-healing process, data change events that occurred during a preceding time horizon are identified, a corresponding first set of data record(s) are identified, a difference between the first set and a second set of data record(s) that successfully synced during the time horizon is determined as a third set of data record(s), and any data record that was attempted to be synced during the time horizon but failed is excluded from the third set. A sync of any data record remaining in the third set is then initiated.

Methods are provided for supervising a motor control unit with at least two separate channels, each of the two channels including at least: means for executing a given application task AS, the application task AS including a plurality of successively executed computations between which latency periods elapse; a first component capable of performing the computations; a second component capable of storing data; the application tasks AS of the channels being capable of communicating. The method comprising includes the following steps: a) detecting a latency period; b) performing, during this latency period, an operating state test of at least one of the components; and c) determining a state of the component corresponding to a failure state or a healthy state.