An electronic circuit includes first and second channels which respectively receive first and second analog signals. The first channel includes a first digital to analog converter having an output coupled to a first input of a first sign comparator, and the second channel includes a second digital to analog converter. A switch network selectively couples, upon reception of a self-test mode signal signaling a test phase, an output of the second digital to analog converter to a second input of the first sign comparator. A ramp generation circuit supplies to the first digital to analog converter and the second digital to analog converter two identical ramps of digital codes, which are shifted by a programmable offset with respect to one another. A checking circuit issues a test status signal based on the output of the first sign comparator.

A device for processing digital signals is provided. The device comprises a digital signal source and a converter circuit having a current supply. The digital signal source outputs a codeword. The converter circuit receives the codeword from the digital signal source, receives a current at the current supply, and generates an output signal based on the codeword. The current is generated in accordance with the codeword.

A device for processing digital signals is provided. The device comprises a digital signal source and a converter circuit having a current supply. The digital signal source outputs a codeword. The converter circuit receives the codeword from the digital signal source, receives a current at the current supply, and generates an output signal based on the codeword. The current is generated in accordance with the codeword.

A self-calibrating digital-to-analog converter (DAC) is disclosed. The self-calibrating DAC includes a DAC including a least significant bit (LSB) side resistor network and a most significant bit (MSB) side resistor network. At least the MSB side resistor network includes a plurality of trimmable resistors. A resistance to frequency converter coupled with an output of the DAC is included to generate a frequency f.sub.L based on a value of the LSB side resistor network or the MSB side resistor network. A monitor is included to generate a counter value by comparing f.sub.L with a high frequency clock having a constant frequency f.sub.H. A memory is included to store at least two counter values generating by comparing f.sub.L and f.sub.H once when the LSB side resistor network is connected while the MSB side resistor network is floating and once when the LSB side resistor network is floating while only one of the resistors in the MSB side resistor network is connected and all other resistors in the MSB side resistor network are floating. A comparator is included to compare the at least two counter values. A trimming controller is included to generate a trimming signal to trim one of the plurality of trimmable resistors based on an output of the comparator.

An Artificial Neural Network (ANN) processing system includes artificial neurons (processing elements) and an analog to digital converter (ADC). An artificial neuron includes a digital to analog converter (DAC) and a low pass filter (LPF) configured to generate a first filtered analog current signal. Also, the artificial neuron includes a delta-sigma DAC configured to generate an M-bit current signal based on a digital weight value. The artificial neuron also includes a multiplier configured to generate a first output current source signal based on the first filtered analog current signal and the M-bit current signal. The ADC is operably coupled to a common node via a single line and configured to generate a digital output signal based on an input voltage of the ADC. The digital output signal is representative of a summation of output analog current signals at a common node to which the ADC is operably coupled.

Embodiments of the present disclosure provide a signal transmitting method. According to the method, in a signal transmitting process, before entering a digital to analog converter (DAC), a first frequency modulated signal of a high-pass channel is first subjected to nonlinear compensation and gain mismatch compensation. In the process, a nonlinear compensation coefficient and a gain mismatch compensation coefficient are determined according to an output voltage of the high-pass channel and an output frequency of a voltage-controlled oscillator (VCO) during a calibration stage.

Embodiments of the present disclosure provide a signal transmitting method. According to the method, in a signal transmitting process, before entering a digital to analog converter (DAC), a first frequency modulated signal of a high-pass channel is first subjected to nonlinear compensation and gain mismatch compensation. In the process, a nonlinear compensation coefficient and a gain mismatch compensation coefficient are determined according to an output voltage of the high-pass channel and an output frequency of a voltage-controlled oscillator (VCO) during a calibration stage.

To prevent occurrence of an input voltage dependent error due to an input parasitic capacitance. A comparator includes: a first transistor and a second transistor that include two sources connected to each other, two gates to which a differential input signal pair are input, and two drains that output a differential output signal pair corresponding to a difference signal of the differential input signal pair; a third transistor that is connected between both the sources of the first transistor and the second transistor and a first reference voltage node, the third transistor being switched on or off in accordance with logic of a first signal; and a fourth transistor that is connected between both the sources of the first transistor and the second transistor and a second reference voltage node, the fourth transistor being switched on or off in accordance with logic of a second signal having logic different from the logic of the first signal.

A mixed signal receiver includes a first sample and hold (S/H) circuit having a first S/H input terminal to receive an analog input signal and a first S/H output terminal directly coupled to a first common node; a first data slicer having a first slicer input terminal coupled to the first common node; and a first data-driven charge coupling digital-to-analog converter (DAC) including: (i) a DAC input terminal to receive a first digital signal from a first digital output of the first data slicer, (ii) a DAC output terminal directly coupled to the first common node, (iii) a plurality of capacitor modules configured to be pre-charged during a sample phase, and (iv) logic components, wherein when the logic components toggle a voltage on the plurality of capacitor modules, charge is capacitively coupled to or from the first common node during an immediately subsequent hold phase.

A mixed signal receiver includes a first sample and hold (S/H) circuit having a first S/H input terminal to receive an analog input signal and a first S/H output terminal directly coupled to a first common node; a first data slicer having a first slicer input terminal coupled to the first common node; and a first data-driven charge coupling digital-to-analog converter (DAC) including: (i) a DAC input terminal to receive a first digital signal from a first digital output of the first data slicer, (ii) a DAC output terminal directly coupled to the first common node, (iii) a plurality of capacitor modules configured to be pre-charged during a sample phase, and (iv) logic components, wherein when the logic components toggle a voltage on the plurality of capacitor modules, charge is capacitively coupled to or from the first common node during an immediately subsequent hold phase.