A fast load current sensing apparatus and scheme provides instantaneous detection of peak current excursions using low silicon area and power efficient techniques. The response time for detecting signal excursions and measuring a signal (e.g., load current) is independent of resolution or precision and can be applied to high resolution telemetry. The apparatus sends out maximum current limit (FHC_limit) code at any instant the load current is detected to be more than a digital-to-analog converter (DAC) code. If the load current is less than the FHC_limit the scheme restores to a next DAC code as per a counter's next value. In case load current is more than FHC_limit, the scheme updates the DAC code to FHC_limit code and starts the counter from the FHC_limit.

A method is disclosed for steering a physical analog system (e.g., an electric motor) using a discrete-level (e.g., binary) control signal. The discrete-level control signal is computed by an iterative scheme that can handle a long planning horizon. A preference for infrequent level switches can be taken into account. The quality of the fit to the target trajectory can be expressed not only by the quadratic error, but also by other norms. The method can be used also for digital-to-analog conversion.

One or more systems, devices and/or methods of use provided herein relate to a device that can support a signal generation. A current-mode end-to-end signal path can include a digital to analog converter (DAC) operating in current-mode and an upconverting mixer, operating in current-mode and operatively coupled to the DAC. Analog inputs and outputs of the DAC and upconverting mixer can be represented as currents, and the DAC can generate a baseband signal. The DAC and upconverting mixer each can comprise switching transistors of the same type, such as p-type metal-oxide semiconductor (PMOS) switching transistors. In one or more embodiments, a current source and a diode-connected transistor can be arranged in parallel in the current-mode signal path, and the current source passes a static current, while the diode-connected transistor passes both a static current and a dynamic current.

One or more systems, devices and/or methods of use provided herein relate to a device that can support a signal generation. A current-mode end-to-end signal path can include a digital to analog converter (DAC) operating in current-mode and an upconverting mixer, operating in current-mode and operatively coupled to the DAC. Analog inputs and outputs of the DAC and upconverting mixer can be represented as currents, and the DAC can generate a baseband signal. The DAC and upconverting mixer each can comprise switching transistors of the same type, such as p-type metal-oxide semiconductor (PMOS) switching transistors. In one or more embodiments, a current source and a diode-connected transistor can be arranged in parallel in the current-mode signal path, and the current source passes a static current, while the diode-connected transistor passes both a static current and a dynamic current.

A phase interpolator with a DAC outputting a first and second value responsive to a control code. A first current mirror generates a first current proportional to the first value. A second current mirror generates a second current proportional to the second value. A first FET pair comprising a first and second FET such that the source terminals of the first FET and the second FET are electrically connected and connect to the first current mirror. A second FET pair comprising a third and fourth FET such that the source terminals of the third FET and the fourth FET are electrically connected and connect to the second current mirror. A first terminal outputs a phase adjusted clock signal as compared to the clock signal, from the first FET and the third FET. A second terminal outputs an inverted phase adjusted clock signal, from the second FET and the fourth FET.

A method may be provided for powering up or down a playback path comprising a digital-to-analog converter (DAC) for generating a non-ground-centered analog intermediate voltage centered at a common-mode voltage and coupled to a driver for generating a ground-centered playback path output voltage at an output of the driver wherein the output of the driver is clamped via a finite impedance to a ground voltage. The method may include transitioning continuously or in a plurality of discrete steps the analog intermediate voltage from an initial voltage to the common-mode voltage such that the transitioning is substantially inaudible at the output of the driver. A method for operating an output clamp of an output driver stage of a playback path may include transitioning continuously or in a plurality of discrete steps an impedance of the output clamp in order to match an output offset of the output driver stage in order to minimize audio artifacts appearing at an output of the output driver stage.

A method of Vernier digital-to-analog conversion, the method including: performing conversion of a reference signal Y using a control code X=M+α.sup.−αN with a length ψ=α+β, wherein M is a control code with a length α, including high-order bits of the control code X, and α.sup.−αN is a control code with a length β, including lower-order bits of the control code X, wherein α≈β; performing digital multiplication of the lower-order a.sup.−αN bits of the control code X by a.sup.α times algebraic summing α of the high-order bits of the control code X and β of the lower-order bits of a.sup.−αN of the control code X being a result of multiplication by a.sup.α times, according to formula Q=M±N, wherein N is a resulting digital code of the digital multiplication, and Q is a resulting digital code of M±N; converting the resulting digital code Q from a reference signal Y.sub.1 to an analog signal Z.sub.1, and converting the resulting digital code N from a reference signal Y.sub.2 to an analog signal Z.sub.2, wherein reference signals Y.sub.1 and Y.sub.2 are related by a ratio: Y.sub.2=Y.sub.1 (1±a.sup.−α), wherein a is a base of number system, α is a number of bits of shifting the control code a.sup.−αN; and summing analog signals Z.sub.1 and Z.sub.2 to generate an analog output signal Z.sub.0.

A method of Vernier digital-to-analog conversion, the method including: performing conversion of a reference signal Y using a control code X=M+α.sup.−αN with a length ψ=α+β, wherein M is a control code with a length α, including high-order bits of the control code X, and α.sup.−αN is a control code with a length β, including lower-order bits of the control code X, wherein α≈β; performing digital multiplication of the lower-order a.sup.−αN bits of the control code X by a.sup.α times algebraic summing α of the high-order bits of the control code X and β of the lower-order bits of a.sup.−αN of the control code X being a result of multiplication by a.sup.α times, according to formula Q=M±N, wherein N is a resulting digital code of the digital multiplication, and Q is a resulting digital code of M±N; converting the resulting digital code Q from a reference signal Y.sub.1 to an analog signal Z.sub.1, and converting the resulting digital code N from a reference signal Y.sub.2 to an analog signal Z.sub.2, wherein reference signals Y.sub.1 and Y.sub.2 are related by a ratio: Y.sub.2=Y.sub.1 (1±a.sup.−α), wherein a is a base of number system, α is a number of bits of shifting the control code a.sup.−αN; and summing analog signals Z.sub.1 and Z.sub.2 to generate an analog output signal Z.sub.0.

One or more example relate, generally, to generating radio frequency (RF) signals. An apparatus may include a signal generator, an amplification stage, and a feedback control loop. The signal generator may generate a pulsed radio frequency (RF) signal at least partially responsive to a digital pulsed waveform defined by one or more commands. The amplification stage may amplify the pulsed RF signal. The feedback control loop may be coupled to the amplification stage to regulate a power level of respective steps of the pulsed RF signal.

One or more example relate, generally, to generating radio frequency (RF) signals. An apparatus may include a signal generator, an amplification stage, and a feedback control loop. The signal generator may generate a pulsed radio frequency (RF) signal at least partially responsive to a digital pulsed waveform defined by one or more commands. The amplification stage may amplify the pulsed RF signal. The feedback control loop may be coupled to the amplification stage to regulate a power level of respective steps of the pulsed RF signal.