A device includes at least two digital-to-analog converters, each digital-to-analog converter having a digital-to-analog converter clock modulator, a system reference clock modulator, and a phase detector to track the phases of the clock and the system reference clock. A method of calibrating a phase detector includes providing a pulse waveform, aligning a phase of a digital-to-analog clock to a phase of an internal system reference clock, aligning a phase of a modulated system reference clock with a phase of a modulated, divided, digital-to-analog clock, storing the aligned phase of the modulated system reference clock as a calibration value, synchronizing the digital-to-analog converters and adjusting the phase of the digital-to-analog converters to a center of a desired phase, and storing the aligned phase of the digital-to-analog converters as a calibration value.

A device includes at least two digital-to-analog converters, each digital-to-analog converter having a digital-to-analog converter clock modulator, a system reference clock modulator, and a phase detector to track the phases of the clock and the system reference clock. A method of calibrating a phase detector includes providing a pulse waveform, aligning a phase of a digital-to-analog clock to a phase of an internal system reference clock, aligning a phase of a modulated system reference clock with a phase of a modulated, divided, digital-to-analog clock, storing the aligned phase of the modulated system reference clock as a calibration value, synchronizing the digital-to-analog converters and adjusting the phase of the digital-to-analog converters to a center of a desired phase, and storing the aligned phase of the digital-to-analog converters as a calibration value.

An input circuitry for receiving an analog input signal comprises: an input transistor configured to receive the analog input signal on a gate terminal of the input transistor wherein the input transistor is connected to a digital component providing a digital signal, and wherein the input transistor is configured to receive the digital signal on a bulk terminal of the input transistor; wherein the input transistor is configured to provide an output current based on the analog input signal and the digital signal, such that the input transistor provides digital-to-analog conversion of the digital signal received on the bulk terminal.

A semiconductor device comprising at least one transmit path is provided. The transmit path comprises an input node for receiving a digital baseband signal. Further, the transmit path comprises digital mixer circuitry coupled to the input node and configured to generate an upconverted digital baseband signal by upconverting a frequency of the digital baseband signal. Additionally, the transmit path comprises Digital-to-Analog Converter (DAC) circuitry coupled to the digital mixer circuitry and configured to generate an analog radio frequency signal based on the upconverted digital baseband signal. The transmit path comprises first analog mixer circuitry coupleable to an output of the DAC circuitry, and second analog mixer circuitry coupleable to the output of the DAC circuitry. Further, the transmit path comprises a first output node coupleable to an output of the first analog mixer circuitry, and a second output node coupleable to an output of the second analog mixer circuitry.

A semiconductor device comprising at least one transmit path is provided. The transmit path comprises an input node for receiving a digital baseband signal. Further, the transmit path comprises digital mixer circuitry coupled to the input node and configured to generate an upconverted digital baseband signal by upconverting a frequency of the digital baseband signal. Additionally, the transmit path comprises Digital-to-Analog Converter (DAC) circuitry coupled to the digital mixer circuitry and configured to generate an analog radio frequency signal based on the upconverted digital baseband signal. The transmit path comprises first analog mixer circuitry coupleable to an output of the DAC circuitry, and second analog mixer circuitry coupleable to the output of the DAC circuitry. Further, the transmit path comprises a first output node coupleable to an output of the first analog mixer circuitry, and a second output node coupleable to an output of the second analog mixer circuitry.

An analog-to-digital conversion system. A clock generator generates a first clock signal at a first frequency. An analog-to-digital converter (ADC) converts an input analog signal to a digital signal. The ADC operates based on the first clock signal at the first frequency. A calibration digital-to-analog converter (DAC) generates an analog reference signal from digital reference data. A fractional rate clock generator generates a second clock signal from the first clock signal. The second clock signal is at a second frequency that is a fractional rate of the first frequency, and the calibration DAC operates at the second frequency. An equalizer processes an output of the ADC to remove a distortion incurred by the ADC and a calibration circuitry generates coefficients for the equalizer based on the digital reference data and the output of the ADC to the analog reference signal.

Digital to analog converters (DAC) are used to convert digital signals to analog values. The digital system providing data to the analog converter may be highly tasked. A DAC is provided with some in built logic to assist in reducing the load on the devices driving the DAC. The DAC may include a library of functions that it can apply to the input words to modify transitions in the analog output words. The DAC may further include a health checking system for monitoring the digital words being supplied to the DAC and raising a concern, and taking action if required, if the sequence of words is unlikely to be correct or beyond the target operating range.

A DAC-based transmit driver architecture with improved bandwidth and techniques for driving data using such an architecture. One example transmit driver circuit generally includes an output node and a plurality of digital-to-analog converter (DAC) slices. Each DAC slice has an output coupled to the output node of the transmit driver circuit and includes a bias transistor having a drain coupled to the output of the DAC slice and a multiplexer having a plurality of inputs and an output coupled to a source of the bias transistor.

A current steering converter fabricated using a predetermined integrated circuit technology includes a unary portion having one or more current sources and a binary portion including a plurality of switches controlled by a decoder, the switches coupled to a converter output; and a plurality of devices commonly connected at a first end and coupled to each respective switch at a second end, wherein each device size comprises (W/L)*M, where W/L is a width and length of the device and M is an integer representing multiple number.

The systems and methods discussed herein utilized a wireless or wired transceiver having a transmitter and a receiver. The transceiver is configured to reduce distortion contributions associated with echo cancelling. The transmitter provides a replica signal and a transmit signal. The replica signal and the transmit signal can be provided using a common switch.