A semiconductor device performs sequential comparison of an analog input signal and a reference voltage to digitally convert the analog input signal. The semiconductor device includes an upper DAC generating a high-voltage region of the reference voltage based on a predetermined code, a lower DAC generating a low-voltage region of the reference voltage based on the code, and an injection DAC having the same configuration as that of the lower DAC and adjusting the low-voltage region of the reference voltage.

A combined I/Q DAC is provided with a plurality of sources corresponding to a plurality of selectors in which the corresponding source drives the corresponding selector with a source signal to produce a corresponding pair of in-phase and quadrature-phase analog input signals to a summation network. Each selector routes its source signal responsive to a digital value of a corresponding in-phase and quadrature-phase bit pair.

A system and method where a comparator is operatively coupled to an output of a Digital-to-analog Converter (DAC). The DAC may comprise a single DAC core or a plurality of interleaved DAC cores. The comparator is configured to capture properties of DAC core output. A digital engine is operatively coupled to receive output of the comparator and configured to calculate a cross-correlation between comparator output and input to the DAC core(s). The digital engine may be configured to determine if the skew of each DAC core is positive or negative and to determine if a skew correction term for the DAC core(s) should be decreased or increased, based on the skew of each DAC core being positive or negative, respectively. In interleaved DAC core devices, clock frequency sampling edges of the comparator may alternate between clock edges of each of the interleaved DAC cores.

A system and method where a comparator is operatively coupled to an output of a Digital-to-analog Converter (DAC). The DAC may comprise a single DAC core or a plurality of interleaved DAC cores. The comparator is configured to capture properties of DAC core output. A digital engine is operatively coupled to receive output of the comparator and configured to calculate a cross-correlation between comparator output and input to the DAC core(s). The digital engine may be configured to determine if the skew of each DAC core is positive or negative and to determine if a skew correction term for the DAC core(s) should be decreased or increased, based on the skew of each DAC core being positive or negative, respectively. In interleaved DAC core devices, clock frequency sampling edges of the comparator may alternate between clock edges of each of the interleaved DAC cores.

The present disclosure relates to the field of analog integrated circuit technology. A digital and analog mixed signal control circuit for eliminating a degenerate metastable state of a self-biased bandgap reference circuit utilizes a digital-to-analog converter module with low-power consumption and flexibly customized accuracy as needed, a delay switch, and a non-volatile memory cell to directly control and clamp a circuit node at the degenerate metastable state in the bandgap reference circuit module, and to release the clamping after a certain delay. Such control mechanism effectively prevents the self-biased bandgap reference circuit with an operational amplifier from entering the degenerate metastable state, and enhance robustness of the circuit, such that the reference circuit is capable of starting normally under various conditions, which improves the performance and yield of the products.

The present disclosure relates to the field of analog integrated circuit technology. A digital and analog mixed signal control circuit for eliminating a degenerate metastable state of a self-biased bandgap reference circuit utilizes a digital-to-analog converter module with low-power consumption and flexibly customized accuracy as needed, a delay switch, and a non-volatile memory cell to directly control and clamp a circuit node at the degenerate metastable state in the bandgap reference circuit module, and to release the clamping after a certain delay. Such control mechanism effectively prevents the self-biased bandgap reference circuit with an operational amplifier from entering the degenerate metastable state, and enhance robustness of the circuit, such that the reference circuit is capable of starting normally under various conditions, which improves the performance and yield of the products.

An audio playback path of an audio apparatus includes a digital modulator, a digital-to-analog converter (DAC), and a power amplifier. The digital modulator receives a playback signal corresponding to playback audio content and generates a digital input signal in accordance with the playback signal. The DAC receives the audio input signal and generates an analog preamplifier signal. The power amplifier generates an audio output signal in accordance with the preamplifier signal and an analog attenuation determined by the analog attenuation signal. The apparatus may include a volume control input to receive a volume control signal and a playback controller configured to perform operations including generating an analog attenuation signal in accordance with the volume control signal, monitoring a playback state indicated by the playback parameters, and responsive to detecting the playback state satisfying the playback criterion, modifying a selected playback parameter to improve a performance parameter of the playback path.

A system includes a first low noise amplifier, a second low noise amplifier, a local analog oscillator signal, a signal splitter, a mixer, a mixer, an analog to digital converter and a digital channelizer. The first low noise amplifier outputs a first amplified analog signal based on a received analog antenna signal at a time t.sub.0. The second low noise amplifier outputs a second amplified analog signal based on the received analog antenna signal at a time t.sub.1. The local analog oscillator signal outputs a local analog oscillator signal. The signal splitter outputs a split analog oscillator signal and a split analog oscillator signal. The mixer outputs a first mixed signal. The mixer outputs a second mixed signal. The analog to digital converter outputs a combined digital signal. The digital channelizer outputs a received signal based on the combined digital signal.

A system includes a first low noise amplifier, a second low noise amplifier, a local analog oscillator signal, a signal splitter, a mixer, a mixer, an analog to digital converter and a digital channelizer. The first low noise amplifier outputs a first amplified analog signal based on a received analog antenna signal at a time t.sub.0. The second low noise amplifier outputs a second amplified analog signal based on the received analog antenna signal at a time t.sub.1. The local analog oscillator signal outputs a local analog oscillator signal. The signal splitter outputs a split analog oscillator signal and a split analog oscillator signal. The mixer outputs a first mixed signal. The mixer outputs a second mixed signal. The analog to digital converter outputs a combined digital signal. The digital channelizer outputs a received signal based on the combined digital signal.

A kickback current is suppressed so as not to generate a deviation in a signal that outputs a comparison result.

A comparator includes a first input terminal and a second input terminal to which a first differential input signal pair is input, a third input terminal and a fourth input terminal to which a second differential input signal pair is input, a first comparison circuit that outputs a signal corresponding to a difference signal of the first differential input signal pair generated by connecting the first input terminal to a positive side and connecting the second input terminal to a negative side and a difference signal of the second differential input signal pair generated by connecting the third input terminal to a positive side and connecting the fourth input terminal to a negative side, and a second comparison circuit that outputs a signal corresponding to a difference signal of the first differential input signal pair generated by connecting the first input terminal to a negative side and connecting the second input terminal to a positive side, and a difference signal of the second differential input signal pair generated by connecting the third input terminal to a positive side and connecting the fourth input terminal to a negative side.