A digital/analog converter (DAC) includes a reference current generator including an internal resistor, and configured to generate reference current according to a resistance value of the internal resistor and a reference voltage, a digital gain block configured to generate a calibrated digital input signal that is obtained by adjusting a digital gain of a digital input signal based on a ratio between a reference resistance value and a resistance value of the internal resistor, and a conversion circuit configured to convert the calibrated digital input signal into an analog output signal, based on the reference current.

A digital/analog converter (DAC) includes a reference current generator including an internal resistor, and configured to generate reference current according to a resistance value of the internal resistor and a reference voltage, a digital gain block configured to generate a calibrated digital input signal that is obtained by adjusting a digital gain of a digital input signal based on a ratio between a reference resistance value and a resistance value of the internal resistor, and a conversion circuit configured to convert the calibrated digital input signal into an analog output signal, based on the reference current.

The disclosure provides a data acquisition device. The data acquisition device includes a sensor that detects a physical quantity as analog data; a digital storage circuit that stores the physical quantity as digital data; a difference circuit that calculates a difference between a previous value of the physical quantity stored in the digital storage circuit and a current value of the physical quantity detected as analog data; and a comparison circuit that compares the difference with a predetermined threshold value; and a control unit. The control unit stores a value calculated by adding or subtracting a predetermined change amount to a previous value of the physical quantity stored in the digital storage circuit as the current value, when the difference exceeds or falls below the threshold value. Since the physical quantity is updated without executing A/D conversion, a decrease in the sampling frequency is suppressed.

A circuit includes a phase-locked loop having a phase-locked loop output to provide a first phase signal and a second phase signal phase delayed with respect to the first phase signal. The circuit further includes a digital circuit having a digital circuit input and an output. The digital circuit input couples to the phase-locked loop output. On the digital circuit output, the digital circuit is configured to provide a first digital-to-analog converter (DAC) enable signal and a second DAC enable signal. The circuit also includes first and second DACs. The first DAC is coupled to the digital circuit. The first DAC has a first enable input coupled to the digital circuit output to receive the first DAC enable signal. The second DAC is coupled to the digital circuit. The second DAC has a second enable input coupled to the digital circuit output to receive the second DAC enable signal.

A circuit includes a phase-locked loop having a phase-locked loop output to provide a first phase signal and a second phase signal phase delayed with respect to the first phase signal. The circuit further includes a digital circuit having a digital circuit input and an output. The digital circuit input couples to the phase-locked loop output. On the digital circuit output, the digital circuit is configured to provide a first digital-to-analog converter (DAC) enable signal and a second DAC enable signal. The circuit also includes first and second DACs. The first DAC is coupled to the digital circuit. The first DAC has a first enable input coupled to the digital circuit output to receive the first DAC enable signal. The second DAC is coupled to the digital circuit. The second DAC has a second enable input coupled to the digital circuit output to receive the second DAC enable signal.

Disclosed are a sound source output apparatus applying a plurality of DACs and an operating method thereof. The sound source output apparatus according to the exemplary embodiment of the present disclosure includes a sound source acquiring unit which acquires a sound source signal; a tag identification processing unit which identifies tag information about the sound source signal; a DAC selection control unit which selects a specific DAC among a plurality of digital analog converters (DACs) based on a tag identification result of the tag information or a user input signal; and a sound source output unit which outputs a sound source which is converted by the selected specific DAC.

Disclosed are a sound source output apparatus applying a plurality of DACs and an operating method thereof. The sound source output apparatus according to the exemplary embodiment of the present disclosure includes a sound source acquiring unit which acquires a sound source signal; a tag identification processing unit which identifies tag information about the sound source signal; a DAC selection control unit which selects a specific DAC among a plurality of digital analog converters (DACs) based on a tag identification result of the tag information or a user input signal; and a sound source output unit which outputs a sound source which is converted by the selected specific DAC.

A pipeline analog to digital converter (ADC) includes converter circuitries, a detector circuitry, and a clock generator circuit. The converter circuitries sequentially convert an input signal to be digital codes. One of the converter circuitries includes a sub-ADC circuit and a multiplying digital to analog converter (MDAC) circuit. The sub-ADC circuit performs a quantization according to a first signal to generate a corresponding one of the digital codes, in which the first signal is the input signal or a previous stage residue signal. The MDAC circuit processes the corresponding one of the digital codes in response to a first clock signal, in order to generate a current stage residue signal. The detector circuitry detects whether the quantization is complete, in order to generate a control signal. The clock generator circuit adjusts a timing of the first clock signal according to the control signal.

A pipeline analog to digital converter (ADC) includes converter circuitries, a detector circuitry, and a clock generator circuit. The converter circuitries sequentially convert an input signal to be digital codes. One of the converter circuitries includes a sub-ADC circuit and a multiplying digital to analog converter (MDAC) circuit. The sub-ADC circuit performs a quantization according to a first signal to generate a corresponding one of the digital codes, in which the first signal is the input signal or a previous stage residue signal. The MDAC circuit processes the corresponding one of the digital codes in response to a first clock signal, in order to generate a current stage residue signal. The detector circuitry detects whether the quantization is complete, in order to generate a control signal. The clock generator circuit adjusts a timing of the first clock signal according to the control signal.

A scaling apparatus and method for compensating nonlinearity due to the finite output impedance of current sources in current-steering digital-to-analog converters (DACs) are disclosed herein. In an example, a DAC may receive a digital input signal. The DAC may determine an output current weight for each of a plurality of unit cells, based on an output impedance of the unit cell. Further, the DAC may generate an analog output signal by applying the plurality of output current weights to the digital input signal. Then, the DAC may output the analog output signal. The analog output signal may be a high frequency analog output signal, which may be an optical high frequency analog output signal. In an example, a transfer curve of the analog output signal may be linear in terms of analog output signal voltage versus digital input code. The output current weights may include one or more polynomial terms.