Methods, systems, and apparatus for quantum analog-digital conversion. In one aspect, a method includes obtaining a quantum analog signal; applying a hybrid analog-digital encoding operation to the quantum analog signal and a qudit in an initial state to obtain an evolved state of the qudit, wherein the hybrid analog-digital encoding operation is based on a swap operation comprising multiple adder operations; and providing the qudit in the evolved state as a quantum digital encoding of the quantum analog signal.

Methods, systems, and apparatus for quantum analog-digital conversion. In one aspect, a method includes obtaining a quantum analog signal; applying a hybrid analog-digital encoding operation to the quantum analog signal and a qudit in an initial state to obtain an evolved state of the qudit, wherein the hybrid analog-digital encoding operation is based on a swap operation comprising multiple adder operations; and providing the qudit in the evolved state as a quantum digital encoding of the quantum analog signal.

A voltage comparator and a programmable counter coupled to a high-speed clock are used to provide a near constant delay time for use in a closed-loop system. The voltage comparator input-output time delay is characterized at a certain temperature and operating voltage then variances in the voltage comparator delay times over a range of operating temperatures and voltages are measured and/or extrapolated. A number of clock pulses used for a delay time count are programmed into the programmable counter to provide for a near constant delay time from a change at the input of the voltage comparator to a change at the output of the programmable counter.

A digital to analog conversion, DAC, device for converting digital signals to analog signals comprises a RF output for outputting the analog signals, a thermometer segment comprising a first number of data slices and a second number calibration slices, and a calibration controller, which electrically disconnects one of the data slices from the RF output and at the same time connects one of the calibration slices to the RF output as replacement slice for the respective data slice and performs a calibration of the disconnected data slice.

A digital to analog conversion, DAC, device for converting digital signals to analog signals comprises a RF output for outputting the analog signals, a thermometer segment comprising a first number of data slices and a second number calibration slices, and a calibration controller, which electrically disconnects one of the data slices from the RF output and at the same time connects one of the calibration slices to the RF output as replacement slice for the respective data slice and performs a calibration of the disconnected data slice.

Noise and distortion reduction in a signal processed through analog circuitry includes providing noise reduction circuitry to reduce signal noise generated by at least one analog circuit element. The noise reduction circuitry is adaptively configured to adjust a rate to apply noise reduction to the signal without introducing unwanted distortion. Distortion reduction circuitry is adaptively configured to adjust a rate to apply distortion reduction to the signal without introducing unwanted noise. The signal is processed through the analog circuitry using the adaptively configured noise reduction circuitry and adaptively configured distortion reduction circuitry to reduce both noise and distortion in the signal.

The disclosure relates to a radar transceiver having a transmitter comprising a phase shifter. Example embodiments include a radar transceiver (200) having a normal mode of transmitter operation and a self-test mode of operation, the transceiver (200) comprising: a digital controller (116) configured to provide a digital control signal indicative of a phase shift; a digital to analogue converter (122) configured to receive the digital control signal and provide an analogue signal in accordance with the phase shift; a phase shifter (124) configured to receive the analogue signal and provide a phase shifted output signal for transmission; a dummy load (240) connected to receive the analogue signal from the digital to analogue converter (122) and to provide an analogue output; a resistor network (331) connected across an output of the dummy load (240); a testing module (335) configured to measure the analogue output of the dummy load (240); and a controller module (339) configured to control operation of the dummy load (240); testing module (335) and digital controller (116) during the self-test mode of operation by: enabling the dummy load (240); operating the digital controller (116) to provide a range of digital control signals to the digital to analogue converter (122); and operate the testing module (335) to measure the analogue output of the dummy load (240) to determine a measure of linearity of the digital to analogue converter (122).

An object is to improve Power Supply Rejection Ratio in a PLL circuit. A proportional path 103 is provided in a first power supply system 101 and outputs analog proportional signal AP according to a detection signal DET. An integral path 104 is provided in a second power supply system and outputs an analog integral signal AI according to the DET. A CCO driver 16 is provided in the first power supply system 101 and outputs control current ICCO according to the AP and the AI. A CCO 17 is provided in the second power supply system 102 and outputs an output signal Fout according to the ICCO. A phase frequency detector 11 is provided in the second power supply system 102 and configured to detect a phase difference between a reference signal Fref and a signal FM obtained by feeding back the Fout and then outputs the DET.

A method in a transmitter circuit of generating a signal comprising a first sequence of OFDM symbols, which are to be transmitted within a frequency sub band of a second sequence of OFDM symbols is disclosed. A first cyclic prefix (CP) of the second sequence of OFDM symbols has a first duration, and a second CP of the second sequence of OFDM symbols has a second duration. In order to generate both the first and the second cyclic prefix with an integer number of equidistant samples, a first sampling rate is required. The method comprises generating the signal comprising the first sequence of OFDM symbols at a second sampling rate, lower than the first sampling rate, and adjusting a sampling phase during CPs.

A built-in-self-test (BIST) circuit is connected to a processor and a sigma-delta modulator (SDM) and includes an averaging circuit, a reference signal generator, and a comparator. The averaging circuit calculates an average of a sum of a set of bit signals of the SDM output signal over a period of time period, and generates an average SDM signal. The reference signal generator generates a reference SDM signal based on an SDM input signal. The comparator compares the voltage levels of the average SDM and reference SDM signals with a threshold value, and generates a test output signal based on the comparison.