There is disclosed herein clock generation circuitry, in particular rotary travelling wave oscillator circuitry. Such circuitry comprises a pair of signal lines connected together to form a dosed loop and arranged such that they define at least one transition section where both said lines in a first portion of the pair cross from one lateral side of both said lines in a second portion of the pair to the other lateral side of both said lines in the second portion of the pair.

A semiconductor device in which variations are controlled is provided. The semiconductor device has a function of converting a digital signal into an analog signal, and includes a digital-analog converter circuit, an amplifier circuit, first to fourth switches, a first output terminal, a second output terminal, and a power source. The amplifier circuit is configured to perform feedback control when the first switch and the fourth switch are on and the second switch and the third switch are off. The amplifier circuit is configured to perform comparison control when the first switch and the fourth switch are off and the second switch and the third switch are on; utilizing this, variations in the digital-analog converter circuit and the amplifier circuit are controlled.

A phase-locked loop (PLL) includes a spur cancellation circuit that receives a residue signal indicative of a first frequency and receives a residual phase error signal and generates a spur cancellation signal. A summing circuit combines the spur cancellation signal and a first phase error signal corresponding to a phase difference between a reference signal and a feedback signal in the PLL and generates a second phase error signal with a reduced spurious tone at the first frequency.

A phase-locked loop (PLL) includes a spur cancellation circuit that receives a residue signal indicative of a first frequency and receives a residual phase error signal and generates a spur cancellation signal. A summing circuit combines the spur cancellation signal and a first phase error signal corresponding to a phase difference between a reference signal and a feedback signal in the PLL and generates a second phase error signal with a reduced spurious tone at the first frequency.

Systems and methods are provided for digital-to-analog converters (DACs) with enhanced dynamic element matching (DEM) and calibration. DEM may be adapted based on assessment of one or more conditions that may affect the DACs or DEM functions thereof. The one or more condition may comprise amount of signal backoff. The adaption may comprise switching the DEM function (as a whole, or partially—e.g., individual DEM elements) on or off based on the assess conditions. The DACs may incorporate use of calibration. The DEM and/or the calibration may be applied to only a portion of the DAC, such as a particular segment (e.g., a middle segment comprising bits between the MSBs and the LSBs).

A filter circuit includes: a division unit that divides an input signal and adds, to a tail end of a division block, of head data of the next division block, to generate an input block; a plurality of signal processing units that perform filtering of a feedback type on input blocks to generate output samples, and generate and output blocks; and a coupling unit that couples the output blocks. The signal processing unit outputs first output samples generated until a switching timing, and outputs second output samples generated by the signal processing unit after the timing. The switching timing is a timing within a period corresponding to the duplicated data, at which timing a difference between a first signal generated by the signal processing unit and a second signal generated by the signal processing unit is less than or equal to a threshold consecutively for a second data length.

A spur correction system for a transmit chain having an interleaving multiplexer. In some embodiments, the spur correction system includes a spur sense chain, a correction controller, and a Q path corrector. The interleaving multiplexer combines signals from multiple bands in response to a clock signal. The spur sense chain estimates an error that is in phase with the clock signal (an I-phase error) and an error that is a derivative of the clock signal (a Q-phase error). The correction controller compensates for the estimated I-phase error by injecting an I-phase correction signal into the transmit chain. The Q path corrector compensates for the estimated Q-phase error by selectively connecting one or more capacitors within the interleaving multiplexer.

A multi-channel digital to analog converter, DAC, comprising: a DAC configured to provide an analog signal comprising a plurality of time division multiplexed sub-signals, each provided for one of a plurality of output channels; wherein each of the output channels include: a sampling capacitor; a selector switch configured to couple the sampling capacitor of the respective output channel to the output terminal of the DAC such that the sampling capacitor samples the analog signal over a plurality of discrete sampling periods; a comparator configured to provide a comparator output signal, wherein the sampling capacitor is coupled to an input terminal of the comparator; and an output control gate configured to control whether or not the comparator output signal is output from the respective output channel at a predetermined time later than a first of the respective plurality of discrete sampling periods.

A multi-channel digital to analog converter, DAC, comprising: a DAC configured to provide an analog signal comprising a plurality of time division multiplexed sub-signals, each provided for one of a plurality of output channels; wherein each of the output channels include: a sampling capacitor; a selector switch configured to couple the sampling capacitor of the respective output channel to the output terminal of the DAC such that the sampling capacitor samples the analog signal over a plurality of discrete sampling periods; a comparator configured to provide a comparator output signal, wherein the sampling capacitor is coupled to an input terminal of the comparator; and an output control gate configured to control whether or not the comparator output signal is output from the respective output channel at a predetermined time later than a first of the respective plurality of discrete sampling periods.

Disclosed herein are related to systems and methods for selectively disabling current steering circuitries. In one aspect, the system includes a balun including a first inductor and a second inductor, a first current steering circuit coupled to the first inductor, a second current steering circuit coupled to the first inductor, and a controller coupled to the first current steering circuit and the second current steering circuit. In one aspect, the controller is configured to, based on input data having a first state, apply a first signal and a second signal having a first level to the first current steering circuit and a third signal and a fourth signal having the first level to the second current steering circuit to disable a first current through the second inductor, a second current through the first current steering circuit, and a third current through the second current steering circuit.