The present invention relates to circuitry comprising: interpolation filter circuitry configured to receive a digital input signal and to output an interpolated digital signal; amplifier circuitry configured to generate an output signal based on the interpolated digital signal; and protection circuitry. The protection circuitry is configured to activate in response to detection of a fault condition at an output of the amplifier circuitry. The circuitry further comprises first detection circuitry configured to output a control signal to disable the protection circuitry on detection of a transient signal at an output of the interpolation filter circuitry that is unrelated to a fault.

A compute-in-memory array is provided in which each neuron includes a capacitor and an output transistor. During an evaluation phase, a filter weight voltage and the binary state of an input bit controls whether the output transistor conducts or is switched off to affect a voltage of a read bit line connected to the output transistor.

A novel and useful quantum computing machine architecture that includes a classic computing core as well as a quantum computing core. A programmable pattern generator executes sequences of instructions that control the quantum core. In accordance with the sequences, a pulse generator functions to generate the control signals that are input to the quantum core to perform quantum operations. A partial readout of the quantum state in the quantum core is generated that is subsequently re-injected back into the quantum core to extend decoherence time. Access gates control movement of quantum particles in the quantum core. Errors are corrected from the partial readout before being re-injected back into the quantum core. Internal and external calibration loops calculate error syndromes and calibrate the control pulses input to the quantum core. Control of the quantum core is provided from an external support unit via the pattern generator or can be retrieved from classic memory where sequences of commands for the quantum core are stored a priori in the memory. A cryostat unit functions to provide several temperatures to the quantum machine including a temperature to cool the quantum computing core to approximately 4 Kelvin.

A novel and useful quantum computing machine architecture that includes a classic computing core as well as a quantum computing core. A programmable pattern generator executes sequences of instructions that control the quantum core. In accordance with the sequences, a pulse generator functions to generate the control signals that are input to the quantum core to perform quantum operations. A partial readout of the quantum state in the quantum core is generated that is subsequently re-injected back into the quantum core to extend decoherence time. Access gates control movement of quantum particles in the quantum core. Errors are corrected from the partial readout before being re-injected back into the quantum core. Internal and external calibration loops calculate error syndromes and calibrate the control pulses input to the quantum core. Control of the quantum core is provided from an external support unit via the pattern generator or can be retrieved from classic memory where sequences of commands for the quantum core are stored a priori in the memory. A cryostat unit functions to provide several temperatures to the quantum machine including a temperature to cool the quantum computing core to approximately 4 Kelvin.

The present invention provides an amplifier including a DAC, an analog signal processing circuit, a digital signal processing circuit, a signal detector and a driving stage is disclosed. The DAC is configured to perform a digital-to-analog conversion operation on a digital input signal to generate an analog input signal. The analog signal processing circuit is configured to generate a first processed signal according to the analog input signal and a feedback signal. The digital signal processing circuit is configured to process the digital input signal to generate a second processed signal. The signal detector is configured to detect strength of the digital input signal to generate a mode selection signal. The driving stage is configured to refer to the mode selection signal to receive one of the first processed signal and the second processed signal to generate an output signal, wherein the feedback signal is generated by the output signal.

The present invention provides an amplifier including a DAC, an analog signal processing circuit, a digital signal processing circuit, a signal detector and a driving stage is disclosed. The DAC is configured to perform a digital-to-analog conversion operation on a digital input signal to generate an analog input signal. The analog signal processing circuit is configured to generate a first processed signal according to the analog input signal and a feedback signal. The digital signal processing circuit is configured to process the digital input signal to generate a second processed signal. The signal detector is configured to detect strength of the digital input signal to generate a mode selection signal. The driving stage is configured to refer to the mode selection signal to receive one of the first processed signal and the second processed signal to generate an output signal, wherein the feedback signal is generated by the output signal.

An apparatus comprises a sigma-delta analog-to-digital converter (ADC) circuit including a serial data input, a serial data output, a serial clock input to receive a serial clock signal, and a master clock input to receive a master clock signal; a digital isolator circuit including outputs coupled to the serial clock input and serial data input of the sigma-delta ADC circuit, and an input coupled to the serial data output of the sigma-delta ADC circuit; an oscillator circuit unconnected to the digital isolator circuit and configured to generate the master clock signal asynchronous to the serial clock input signal; and wherein the sigma-delta ADC circuit generates an ADC sampling clock using the master clock.

A fast load current sensing apparatus and scheme provides instantaneous detection of peak current excursions using low silicon area and power efficient techniques. The response time for detecting signal excursions and measuring a signal (e.g., load current) is independent of resolution or precision and can be applied to high resolution telemetry. The apparatus sends out maximum current limit (FHC_limit) code at any instant the load current is detected to be more than a digital-to-analog converter (DAC) code. If the load current is less than the FHC_limit the scheme restores to a next DAC code as per a counter's next value. In case load current is more than FHC_limit, the scheme updates the DAC code to FHC_limit code and starts the counter from the FHC_limit.

An optical receiver device includes a boost converter circuit, an optical receiver circuit, and a pulse width modulation controller circuitry. The boost converter circuit is configured to convert a supply voltage according to a pulse width modulation signal, in order to generate an output voltage. The optical receiver circuit is configured to set a gain according to the output voltage, in order to convert an optical signal to a data signal according to the gain. The pulse width modulation controller circuitry is configured to perform a digital to analog conversion according to a control code to gradually adjust a current associated with the output voltage, and to compare the output voltage with a reference voltage to generate the pulse width modulation signal.

An optical receiver device includes a boost converter circuit, an optical receiver circuit, and a pulse width modulation controller circuitry. The boost converter circuit is configured to convert a supply voltage according to a pulse width modulation signal, in order to generate an output voltage. The optical receiver circuit is configured to set a gain according to the output voltage, in order to convert an optical signal to a data signal according to the gain. The pulse width modulation controller circuitry is configured to perform a digital to analog conversion according to a control code to gradually adjust a current associated with the output voltage, and to compare the output voltage with a reference voltage to generate the pulse width modulation signal.