A frequency synthesizer includes a phase-locked loop (PLL). The PLL includes a first voltage-controlled oscillator (VCO) and a second VCO, each comprising an oscillator, a capacitor bank, and a bias circuit. The capacitor bank is configured to selectably adjust an output frequency of the oscillator. The bias circuit is configured to provide a bias current to the oscillator, and includes a current digital-to-analog converter (IDAC), and an amplifier coupled to the IDAC and configured to drive the oscillator.

A frequency synthesizer includes a phase-locked loop (PLL). The PLL includes a first voltage-controlled oscillator (VCO) and a second VCO, each comprising an oscillator, a capacitor bank, and a bias circuit. The capacitor bank is configured to selectably adjust an output frequency of the oscillator. The bias circuit is configured to provide a bias current to the oscillator, and includes a current digital-to-analog converter (IDAC), and an amplifier coupled to the IDAC and configured to drive the oscillator.

An IP speaker system is disclosed that includes an IP speaker connected to one or more external analog speakers. The IP speaker comprises a CPU that provides an audio data stream for transmission to a first amplifier and a second amplifier. The first amplifier outputs a first analog audio signal at a first power level for driving an internal driver of the IP speaker, and the second amplifier outputs a second analog audio signal at a second power level for driving one or more external drivers of the one or more external analog speakers. The CPU supervises the one or more external analog speakers so as to detect any speaker failure, disconnection, short or other change in operational status. The IP speaker also comprises a power circuit that receives electrical power transmitted over a network cable as its input power and provides output power available for consumption by the IP speaker and the one or more external analog speakers. The power circuit measures the input power and decreases the output power if the measured input power exceeds a predetermined power level.

An IP speaker system is disclosed that includes an IP speaker connected to one or more external analog speakers. The IP speaker comprises a CPU that provides an audio data stream for transmission to a first amplifier and a second amplifier. The first amplifier outputs a first analog audio signal at a first power level for driving an internal driver of the IP speaker, and the second amplifier outputs a second analog audio signal at a second power level for driving one or more external drivers of the one or more external analog speakers. The CPU supervises the one or more external analog speakers so as to detect any speaker failure, disconnection, short or other change in operational status. The IP speaker also comprises a power circuit that receives electrical power transmitted over a network cable as its input power and provides output power available for consumption by the IP speaker and the one or more external analog speakers. The power circuit measures the input power and decreases the output power if the measured input power exceeds a predetermined power level.

A phased array receiver can include a plurality of antennas, a plurality of compound analog-to-digital converters and a beam former. The plurality of antennas can be arranged in an array. The plurality of compound analog-to-digital converters can include respective inputs coupled to respective ones of the plurality of antennas. Respective output of the plurality of compound analog-to-digital converters can be coupled to the beam former. Each compound analog-to-digital converter can include a plurality of time interleaved sub-analog-to-digital converters. Sampling by the sub-analog-to-digital converters can be random between the sub-analog-to-digital converters within respective compound analog-to-digital converters and random between the plurality of compound analog-to-digital converters. In addition, dynamic element mismatch using a random bitstream generator can be employed in digital-to-analog converters and analog-to-digital converters.

Apparatuses and methods of current balancing, current sensing and phase balancing, offset cancellation, digital to analog current converter with monotonic output using binary coded input (without binary to thermometer decoder), compensator for a voltage regulator (VR), etc. In one example, a plurality of inductors is coupled to a capacitor and a load; a plurality of bridges, each of which is coupled to a corresponding inductor from the plurality of inductors; and a plurality of current sensors, each of which is coupled to a bridge to sense current through a transistor of the bridge

Apparatuses and methods of current balancing, current sensing and phase balancing, offset cancellation, digital to analog current converter with monotonic output using binary coded input (without binary to thermometer decoder), compensator for a voltage regulator (VR), etc. In one example, a plurality of inductors is coupled to a capacitor and a load; a plurality of bridges, each of which is coupled to a corresponding inductor from the plurality of inductors; and a plurality of current sensors, each of which is coupled to a bridge to sense current through a transistor of the bridge

The present invention provides a device for processing digital signals. The device comprises a digital signal source configured to output codewords, a converter circuit configured to generate an output signal based on a first codeword received from the digital signal source, and a feed forward circuit configured to generate an output current based on a second codeword received from the digital signal source. The output current generated by the feed forward circuit is connected to a current supply of the converter circuit. The digital signal source is configured to generate the second codeword based on the first codeword in order to compensate for variations of a supply current of the converter circuit.

The present invention provides a device for processing digital signals. The device comprises a digital signal source configured to output codewords, a converter circuit configured to generate an output signal based on a first codeword received from the digital signal source, and a feed forward circuit configured to generate an output current based on a second codeword received from the digital signal source. The output current generated by the feed forward circuit is connected to a current supply of the converter circuit. The digital signal source is configured to generate the second codeword based on the first codeword in order to compensate for variations of a supply current of the converter circuit.

A digital-to-analog conversion circuit includes an operational amplification module having an operational amplifier connected to an output transistor to form a negative feedback circuit to obtain equal voltages at positive and negative ends. A negative end current flowing into the negative end is proportional to a positive end current flowing into the positive end. An input end of a conversion module is connected in parallel with a first resistor of the operational amplification module to obtain the same voltage as the first resistor, and an analog current proportional to the negative end current and positive end current. An output end of the conversion module is connected with the source of the output transistor and configured to receive the analog current and to make the analog current flow to an output resistor via the drain of the output transistor, to obtain an output current proportional to the positive end current.