A mixed signal receiver includes a first sample and hold (S/H) circuit having a first S/H input terminal to receive an analog input signal and a first S/H output terminal directly coupled to a first common node; a first data slicer having a first slicer input terminal coupled to the first common node; and a first data-driven charge coupling digital-to-analog converter (DAC) including: (i) a DAC input terminal to receive a first digital signal from a first digital output of the first data slicer, (ii) a DAC output terminal directly coupled to the first common node, (iii) a plurality of capacitor modules configured to be pre-charged during a sample phase, and (iv) logic components, wherein when the logic components toggle a voltage on the plurality of capacitor modules, charge is capacitively coupled to or from the first common node during an immediately subsequent hold phase.

A mixed signal receiver includes a first sample and hold (S/H) circuit having a first S/H input terminal to receive an analog input signal and a first S/H output terminal directly coupled to a first common node; a first data slicer having a first slicer input terminal coupled to the first common node; and a first data-driven charge coupling digital-to-analog converter (DAC) including: (i) a DAC input terminal to receive a first digital signal from a first digital output of the first data slicer, (ii) a DAC output terminal directly coupled to the first common node, (iii) a plurality of capacitor modules configured to be pre-charged during a sample phase, and (iv) logic components, wherein when the logic components toggle a voltage on the plurality of capacitor modules, charge is capacitively coupled to or from the first common node during an immediately subsequent hold phase.

A digital-to-analog conversion circuit, a digital-to-analog conversion method, and a display device are provided. The digital-to-analog conversion circuit includes a first digital-to-analog conversion sub-circuit and a second digital-to-analog conversion sub-circuit. The second digital-to-analog conversion sub-circuit includes least-significant-bit voltage selection modules whose quantity is a, a weighed summation operational amplifier, switching control modules whose quantity is a and energy storage modules whose quantity is a. The weighted summation operational amplifier includes a reverse-phase input end, an operational amplification output end, and same-phase input ends whose quantity is a. The reverse-phase input end is connected to the operational amplification output end, and a is an integer greater than 1. The weighted summation operational amplifier is configured to perform weighted summation on voltages inputted by the a same-phase input ends at a digital-to-analog conversion stage to acquire an analog voltage, and output the analog voltage via the operational amplification output end.

A digital-to-analog conversion circuit, a digital-to-analog conversion method, and a display device are provided. The digital-to-analog conversion circuit includes a first digital-to-analog conversion sub-circuit and a second digital-to-analog conversion sub-circuit. The second digital-to-analog conversion sub-circuit includes least-significant-bit voltage selection modules whose quantity is a, a weighed summation operational amplifier, switching control modules whose quantity is a and energy storage modules whose quantity is a. The weighted summation operational amplifier includes a reverse-phase input end, an operational amplification output end, and same-phase input ends whose quantity is a. The reverse-phase input end is connected to the operational amplification output end, and a is an integer greater than 1. The weighted summation operational amplifier is configured to perform weighted summation on voltages inputted by the a same-phase input ends at a digital-to-analog conversion stage to acquire an analog voltage, and output the analog voltage via the operational amplification output end.

An architecture for a multichannel geophysical data acquisition system is provided in the field of electrical resistivity tomography. Individual and autonomous node operating systems are provided. Separate communication channels for upstream and downstream data transfer, high voltage transfer and synchronization signals are provided. A novel use of high voltage isolation barriers is also provided. A direct memory access data transfer process is provided.

An architecture for a multichannel geophysical data acquisition system is provided in the field of electrical resistivity tomography. Individual and autonomous node operating systems are provided. Separate communication channels for upstream and downstream data transfer, high voltage transfer and synchronization signals are provided. A novel use of high voltage isolation barriers is also provided. A direct memory access data transfer process is provided.

A controllable temperature coefficient bias (CTCB) circuit is disclosed. The CTCB circuit can provide a bias to an amplifier. The CTCB circuit includes a variable with temperature (VWT) circuit having a reference circuit and a control circuit. The control circuit has a control output, a first current control element and a second current control element. Each current control element has a “controllable” resistance. One of the two current control elements may have a relatively high temperature coefficient and another a relatively low temperature coefficient. A controllable resistance of one of the current control elements increases when the controllable resistance of the other current control element decreases. However, the “total resistance” of the current control circuit remains constant with a constant temperature. The VWT circuit has an output with a temperature coefficient that is determined by the relative amount of current that flows through each current control element of the control circuit. A Current Digital to Analog Converter (IDAC) scales the output of the VWT and provides the scaled output to an amplifier bias input.

A controllable temperature coefficient bias (CTCB) circuit is disclosed. The CTCB circuit can provide a bias to an amplifier. The CTCB circuit includes a variable with temperature (VWT) circuit having a reference circuit and a control circuit. The control circuit has a control output, a first current control element and a second current control element. Each current control element has a “controllable” resistance. One of the two current control elements may have a relatively high temperature coefficient and another a relatively low temperature coefficient. A controllable resistance of one of the current control elements increases when the controllable resistance of the other current control element decreases. However, the “total resistance” of the current control circuit remains constant with a constant temperature. The VWT circuit has an output with a temperature coefficient that is determined by the relative amount of current that flows through each current control element of the control circuit. A Current Digital to Analog Converter (IDAC) scales the output of the VWT and provides the scaled output to an amplifier bias input.

The disclosure discloses a temperature compensation circuit and method for a neural network computing-in-memory array. Reference arrays sparsely inserted in the computing-in-memory array are adopted to provide a reference voltage for ADCs, so that an input voltage and a reference voltage of the ADCs have a same temperature coefficient. Finally, after analog-to-digital conversion by the ADC, the digital output of the ADC is not affected by the external temperature, thereby ensuring the operational precision of the neural network. According to the temperature compensation circuit of the disclosure, the reference arrays have the same structure as the computing-in-memory array. The insertion density of the reference arrays is related to the temperature field where the computing-in-memory arrays are located. One reference array may provide the reference voltage of the ADC for a plurality of computing-in-memory arrays, thereby minimizing the increase of area and power consumption caused by inserting the reference arrays.

A circuit for an I/O module, the circuit having a communication unit for receiving process data, which is connectable to a bus for communication purposes, a microcontroller which is connected to the communication unit, a load, a digital/analog converter, which includes a current output driver for outputting an output current to the load, and a first DC/DC converter. The microcontroller is connected to the digital/analog converter via a digital interface and is configured to set the output current of the digital/analog converter via the digital interface based on the received process data. The microcontroller is configured to output a control signal to a first DC/DC converter via the control interface for setting the first supply voltage based on the output current and the digital voltage value.