An analog-to-digital converter system includes a digital-to-analog converter for generating calibration voltages based on digital input codes, and an analog-to-digital converter, connected to the digital-to-analog converter, for receiving the calibration voltages from the digital-to-analog converter, for receiving sampled voltages, for generating digital output codes based on the calibration voltages, and for generating digital output codes based on the sampled voltages. The analog-to-digital converter system may have a lookup table, connected to the analog-to-digital converter, for storing the first digital output codes in association with the digital input codes. A method of calibrating an analog-to-digital converter system is also disclosed.

Systems, apparatuses, and methods related to a neuron built with posits are described. An example system may include a memory device and the memory device may include a plurality of memory cells. The plurality of memory cells can store data including a bit string in an analog format. A neuromorphic operation can be performed on the data in the analog format. The example system may include an analog to digital converter coupled to the memory device. The analog to digital converter may convert the bit string in the analog format stored in at least one of the plurality of memory cells to a format that supports arithmetic operations to a particular level of precision.

Systems, apparatuses, and methods related to a neuron built with posits are described. An example system may include a memory device and the memory device may include a plurality of memory cells. The plurality of memory cells can store data including a bit string in an analog format. A neuromorphic operation can be performed on the data in the analog format. The example system may include an analog to digital converter coupled to the memory device. The analog to digital converter may convert the bit string in the analog format stored in at least one of the plurality of memory cells to a format that supports arithmetic operations to a particular level of precision.

A digital clock data recovery circuit including: a first vote circuit connected at an output of a first deserializer and configured to generate an even up/down signal based on even deserialized signals from the first deserializer; a first digital to analog converter (DAC) connected at an output of the first vote circuit and configured to control a voltage and/or frequency of a voltage controlled oscillator (VCO) based on the even up/down signal from the first vote circuit; a second vote circuit connected at an output of a second deserializer and configured to generate an odd up/down signal based on odd deserialized signals from the second deserializer; and a second DAC connected at an output of the second vote circuit and configured to control the voltage and/or frequency of the VCO based on the odd up/down signal from the second vote circuit.

A digital clock data recovery circuit including: a first vote circuit connected at an output of a first deserializer and configured to generate an even up/down signal based on even deserialized signals from the first deserializer; a first digital to analog converter (DAC) connected at an output of the first vote circuit and configured to control a voltage and/or frequency of a voltage controlled oscillator (VCO) based on the even up/down signal from the first vote circuit; a second vote circuit connected at an output of a second deserializer and configured to generate an odd up/down signal based on odd deserialized signals from the second deserializer; and a second DAC connected at an output of the second vote circuit and configured to control the voltage and/or frequency of the VCO based on the odd up/down signal from the second vote circuit.

A system includes a plurality of digital-to-analog converter (DAC) channels. Each DAC channel includes a current control circuit which receives a start limit signal or an end limit signal. The current control circuit reduces an output current limit of the channel responsive to the start limit signal and increases the output current limit responsive to the end limit signal. Each channel includes a current sensor circuit adapted to measure the output current of the channel and provide a channel over-current alert signal if the output current rises above a high current limit. The system includes a controller which asserts the start limit signal if the number of channels exceeding the high current limit is greater than a maximum allowable number and asserts the end limit signal if the number of channels exceeding the high current limit is less than the maximum allowable number minus a hysteresis value.

An interdigital capacitor and a multiplying digital-to-analog conversion circuit are provided. The interdigital capacitor includes at least one first metal layer. The following components are disposed in each first metal layer: a first electrode; at least one first finger metal connected to the first electrode; a second electrode; and a plurality of second finger metals connected to the second electrode, and at least one third finger metal connected to the second electrode. The at least one first finger metal is alternately disposed with the plurality of second finger metals to form capacitors, and the at least one third finger metal is a dummy (dummy) finger metal.

An interdigital capacitor and a multiplying digital-to-analog conversion circuit are provided. The interdigital capacitor includes at least one first metal layer. The following components are disposed in each first metal layer: a first electrode; at least one first finger metal connected to the first electrode; a second electrode; and a plurality of second finger metals connected to the second electrode, and at least one third finger metal connected to the second electrode. The at least one first finger metal is alternately disposed with the plurality of second finger metals to form capacitors, and the at least one third finger metal is a dummy (dummy) finger metal.

A nicotine delivery device (200) for generating a mist containing nicotine for inhalation by a user. The device comprises a mist generator device (201) and a driver device (202). The driver device (202) is configured to drive the mist generator device (201) at an optimum frequency to maximise the efficiency of mist generation by the mist generator device (201).

Methods of nonlinear differentiation and nonlinear differentiators are described. A log-sign nonlinear differentiator and an adaptive gain log-sign differentiator for signal tracking in a digital signal processor receive an input signal, u(t), estimates a filtered first state, x.sub.1(t) of the input signal, estimates second state signal, x.sub.2(t), and receive parameters which cause the filtered first state, x.sub.1(t), to converge asymptotically to the input signal, u(t), and the second state signal, x.sub.2(t), to converge asymptotically to the first derivative {dot over (u)}(t) of the input signal, u(t), such that a first output, y.sub.1(t), of the log-sign nonlinear differentiator, is an estimate of the input signal, u(t), and a second output, y.sub.2(t) equals the first derivative, {dot over (u)}(t) of the input signal, u(t), tracked by the log-sign nonlinear differentiator. The adaptive log-sign differentiator includes a signal path which includes calculating a deadzone function at the input of the first differentiator.