A semiconductor device includes a semiconductor substrate, a gate insulator provided on a surface of the semiconductor substrate, a bonding film, including silicon or aluminum, provided on the gate insulator, and a gate pad layer provided above the bonding film, wherein the gate pad layer includes titanium in at least a region in contact with the bonding film.

High power transistors, such as high power gallium nitride (GaN) transistors, are described. These high power transistors have larger total gate widths than conventional high power transistors by arranging multiple linear arrays of gate, drain, and source contacts in parallel. Thereby, the total gate width and the power rating of the high power transistor may be increased without elongating the die of the high power transistor. Accordingly, the die of the high power transistor may be mounted in a smaller circuit package relative to conventional dies with the same power rating.

A semiconductor device includes a semiconductor substrate, a first current-carrying electrode, a second current-carrying electrode, a first control electrode disposed between the first current-carrying electrode and the second current-carrying electrode, a third current-carrying electrode electrically coupled to the first current-carrying electrode, and a fourth current-carrying electrode adjacent the third current-carrying electrode. The third current-carrying electrode and the fourth current-carrying electrode are configured to support current flow from the third current-carrying electrode to the fourth current-carrying electrode parallel to a second direction. The fourth current-carrying element is electrically coupled to the second current-carrying electrode and a second control electrode. The second control electrode is electrically coupled to the first control electrode. A first crossing region is electrically coupled to the first control electrode and a second crossing region is electrically coupled to the fourth current-carrying electrode, wherein the second crossing region crosses a portion of the first crossing region.

A power amplification device includes: a first semiconductor chip including a first main surface and a second main surface; a first field-effect transistor, a first drain finger part, a plurality of first gate finger parts, and a source finger part; a sub-mount substrate including a third main surface and a fourth main surface; and a first filled via provided penetrating from the third main surface to the fourth main surface. In plan view, the first filled via has a rectangular shape. A long side direction of the first filled via is parallel to a long side direction of the plurality of first gate finger parts. In plan view, the first filled via is positioned to overlap part of one first gate finger part included in the plurality of first gate finger parts.

A semiconductor device includes a first layer that contains gold (Au) and is formed on one surface of a semiconductor substrate and a second layer that contains nickel (Ni) and is formed on the first layer. The semiconductor device is provided with a via hole that passes through the second layer, the first layer, and the semiconductor substrate from one surface to another surface opposite thereto, and a via wiring is formed on the inner surface of the via hole. The second layer is a mask used when the semiconductor substrate is etched to form the via hole, and the first layer is a base layer for forming the second layer on the semiconductor substrate. By using an Au-containing layer as the first layer, side etching on the first layer is prevented when the semiconductor substrate is etched, and disconnection of the via wiring is prevented.

A transistor device includes a field plate that extends from a source runner layer and/or a source contact layer. The field plate can be coplanar with and/or below a gate runner layer. The gate runner layer is routed away from a region directly above the gate metal layer by a gate bridge, such that the field plate can extend directly above the gate metal layer without being interfered by the gate runner layer. Coplanar with the source runner layer or the source contact layer, the field plate is positioned close to the channel region, which helps reduce its parasitic capacitance. By vertically overlapping the metal gate layer and the field plate, the disclosed HEMT device may achieve significant size efficiency without additional routings.

RF transistor amplifiers include an RF transistor amplifier die having a semiconductor layer structure, a coupling element on an upper surface of the semiconductor layer structure, and an interconnect structure on an upper surface of the coupling element so that the RF transistor amplifier die and the interconnect structure are in a stacked arrangement. The coupling element includes a first shielded transmission line structure.

A semiconductor package includes a semiconductor die having a semiconductor device, and first and second contact pads arranged on opposite surfaces of the die. The semiconductor die is embedded in a dielectric layer. The semiconductor package also includes one or more first package contact pads and one or more second package contact pads arranged on a first major surface of the semiconductor package. The first contact pad of the die is coupled to the one or more first package contact pads, and the second contact pad of the die is coupled to the one or more second package contact pads. In operation, the semiconductor device causes a current path between the first contact pad and the second contact pad. The package contact pads are arranged on the first major surface of the semiconductor package to provide multiple non-parallel current paths.

Provided is a semiconductor device including: a semiconductor chip having a rectangular region including a first corner portion having a first notch portion, a second corner portion being provided to diagonally face the first corner portion, a third corner portion, and a fourth corner portion being provided to diagonally face the third corner portion on a surface and having a semiconductor element formed in the rectangular region; a first electrode including a fifth corner portion being provided on the first corner portion and having a second notch portion, a sixth corner portion being provided on the second corner portion, a seventh corner portion being provided on the third corner portion, and an eighth corner portion being provided on the fourth corner portion, the first electrode being provided on the semiconductor element, and the first electrode being electrically connected to the semiconductor element; and a first connector including a ninth corner portion being provided on the fifth corner portion and having a third notch portion and a twelfth corner portion being provided on the eighth corner portion, the first connector being provided on the first electrode, and the first connector being electrically connected to the first electrode.

A portion of a source pad is exposed in an opening of a passivation film. In the exposed portion of the source pad, a wiring region in which a package wiring member is to be bonded and a probe region that is a region different from the wiring region are provided. The probe region has a probe mark of a probe for an energization inspection. An area of the probe mark that overlaps the wiring region is at most 30% of an entire area of the wiring region in a plan view of the silicon carbide semiconductor device.