A multi-cell transistor includes a semiconductor structure, a plurality of unit cell transistors that are electrically connected in parallel, each unit cell transistor extending in a first direction in the semiconductor structure, wherein the unit cell transistors are spaced apart from each other along a second direction, and an isolation structure that is positioned between a first group of the unit cell transistors and a second group of the unit cell transistors and that extends above the semiconductor structure.

Embedded die packaging for high voltage, high temperature operation of power semiconductor devices is disclosed, wherein a power semiconductor die is embedded in laminated body comprising a layer stack of a plurality of dielectric layers and electrically conductive layers. For example, the dielectric layers comprise dielectric build-up layers of filled or fiber reinforced dielectric and conductive interconnect comprises copper layers and copper filled vias. Where a solder resist coating is provided, a dielectric build-up layer, e.g. filled or glass fiber reinforced epoxy, is provided between the solder resist coating and underlying copper interconnect, particularly in regions which experience high electric field during operation, such as between closely spaced source and drain interconnect metal. For example, the power semiconductor device comprises a GaN HEMT rated for operation at ≥100V wherein the package body has a laminated structure configured for high voltage, high temperature operation with improved reliability.

A transistor package having four terminals includes a semiconductor transistor chip and a semiconductor diode chip. The semiconductor transistor chip includes a control electrode and a first load electrode on a first surface and a second load electrode on a second surface opposite the first surface. The semiconductor diode chip includes a first diode electrode on a first surface and a second diode electrode on a second surface opposite the first surface. The transistor package includes a first terminal electrically connected to the control electrode, a second terminal electrically connected to the first diode electrode, a third terminal electrically connected to the first load electrode and a fourth terminal electrically connected to the second load electrode. At least the first terminal, the second terminal and the third terminal protrude from one side of transistor package. The first terminal is arranged between the second terminal and the third terminal.

A semiconductor device includes a source bus bar provided on a first surface of a substrate and overlapping with a first via hole penetrating through the substrate, a plurality of first transistors arranged in a second direction intersecting a first direction, each of the first transistors including a first source finger, a first drain finger and a first gate finger which extend in the first direction on the first surface, the first source finger being electrically connected to the source bus bar, and a plurality of second transistors arranged in the second direction, each of the second transistors including a second source finger, a second drain finger and a second gate finger which extend in the first direction on the first surface, the second source finger being electrically connected to the source bus bar, the first transistors and the second transistors sandwiching the source bus bar.

It is an object of the present invention to provide a semiconductor device having high heat dissipation performance. A semiconductor device includes: a diamond substrate having a recess in an upper surface thereof; a nitride semiconductor layer disposed within the recess in the upper surface of the diamond substrate; and an electrode disposed on the nitride semiconductor layer, wherein the nitride semiconductor layer and the electrode constitute a field-effect transistor, the diamond substrate has a source via hole extending through a thickness of the diamond substrate to expose the source electrode, and the semiconductor device further includes a via metal covering an inner wall of the source via hole and a lower surface of the diamond substrate.

According to one embodiment, a semiconductor device includes: a semiconductor layer including a first plane extending along a plane including a first axis and a second axis; a first electrode extending along the first axis; a second electrode extending along the second axis; and a third electrode above the first plane. The third electrode is electrically coupled to the first electrode and the second electrode, and includes a first portion, a second portion and a third portion. The first portion crosses the first electrode. The second portion crosses the second electrode. The third portion crosses the second electrode and is separate at a first end from the second portion.

Representative techniques and devices including process steps may be employed to mitigate the potential for delamination of bonded microelectronic substrates due to metal expansion at a bonding interface. For example, a metal pad may be disposed at a bonding surface of at least one of the microelectronic substrates, where the contact pad is positioned offset relative to a TSV in the substrate and electrically coupled to the TSV.

A transistor device structure may include a submount, a transistor device on the carrier submount, and a metal bonding layer between the submount and the transistor die, the metal bonding stack providing mechanical attachment of the transistor die to the submount. The metal bonding stack may include gold, tin and nickel. A weight percentage of a combination of nickel and tin in the metal bonding layer is greater than 50 percent and a weight percentage of gold in the metal bonding layer is less than 25 percent.

A lateral power semiconductor device structure comprises a pad-over-active topology wherein on-chip interconnect metallization and contact pad placement is optimized to reduce interconnect resistance. For a lateral GaN HEMT, wherein drain, source and gate finger electrodes extend between first and second edges of an active region, the source and drain buses run across the active region at positions intermediate the first and second edges of the active region, interconnecting first and second portions of the source fingers and drain fingers which extend laterally towards the first and second edges of the active region. External contact pads are placed on the source and drain buses. For a given die size, this interconnect structure reduces lengths of current paths in the source and drain metal interconnect, and provides, for example, at least one of lower interconnect resistance, increased current capability per unit active area, and increased active area usage per die.

A high electron mobility transistor (HEMT) includes a channel layer comprising a group III-V compound semiconductor; a barrier layer comprising the group III-V compound semiconductor on the channel layer; a gate electrode on the barrier layer; a source electrode over gate electrode; a drain electrode spaced apart from the source electrode; and a metal wiring layer. A same layer of the metal wiring layer includes a gate wiring connected to the gate electrode, a source field plate connected to the source electrode, and a drain field plate connected to the drain electrode.