Examples of integrated semiconductor devices are described. In one example, an integrated device includes first and second transistors formed on a substrate, where the transistors share a terminal metal feature to reduce a size of the integrated device. The terminal metal feature can include a shared source electrode metalization, for example, although other electrode metalizations can be shared. In other aspects, a first width of a gate of the first transistor can be greater than a second width of a gate of the second transistor, and the shared metalization can taper from the first width to the second width. The integrated device can also include a metal ground plane on a backside of the substrate, and the terminal metal feature can also include an in-source via for the shared source electrode metalization. The in-source via can electrically couple the shared source electrode metalization to the metal ground plane.

A semiconductor device includes an active region formed in a substrate. The active region includes input fingers, output fingers, and common fingers disposed within the substrate and oriented substantially parallel to one another. An input port is electrically connected to the input fingers and an output port is electrically connected to the output fingers. A common region is electrically connected to the common fingers. At least one of the input and output ports is positioned within the active region between the input, output, and common fingers. The common region is interposed between a pair of the common fingers such that the common fingers of the pair are spaced apart by a gap, and at least one of the input and output ports is position in the gap.

A semiconductor device includes first, second and third trenches formed in a semiconductor layer having a first conductivity type. Each trench includes a corresponding field plate and a corresponding gate over each field plate. A first body region having a second opposite conductivity type is between the first and second gates, and a second body region having the second conductivity type is located between the second and third gates. A first source region is located over the first body region and a second source region is located over the second body region, the first and second source regions having the first conductivity type. A first gate bus is conductively connected to the first gate and a second gate bus is conductively connected to the second gate, the first gate bus conductively isolated from the second gate bus.

A semiconductor device includes a gate wiring line connected to an input wiring line, a first and second transistors disposed on both sides of the gate wiring line, and a signal combining wiring line. The signal combining wiring line includes a first output wiring line that extends on or above the first transistor over at least one source wiring line and at least one gate electrode and that is connected to drain wiring lines of the first transistor, a second output wiring line that extends on or above the second transistor over at least one source wiring line and at least one gate electrode and that is connected to drain wiring lines of the second transistor, a third output wiring line that connects the first and the second output wiring lines, and a fourth output wiring line that connects the third output wiring line to the output terminal.

A transistor amplifier includes a die comprising a gate terminal, a drain terminal, and a source terminal, a circuitry module on the transistor die and electrically coupled to the gate terminal, the drain terminal, and/or the source terminal, and one or more passive electrical components on a first surface of the circuitry module. The one or more passive electrical components are electrically coupled between the gate terminal and a first lead of the transistor amplifier and/or between the drain terminal and a second lead of the transistor amplifier.

In a general aspect, a semiconductor device can include a plurality of vertical transistor segments disposed in an active region of a semiconductor region. The plurality of vertical transistor segments can include respective gate electrodes. A first dielectric can be disposed on the active region. An electrically conductive grid can be disposed on the first dielectric. The electrically conductive grid can be electrically coupled with the respective gate electrodes using a plurality of conductive contacts formed through the first dielectric. A second dielectric can be disposed on the electrically conductive grid and the first dielectric. A conductive metal layer can be disposed on the second dielectric layer. The conductive metal layer can include a portion that is electrically coupled with the respective gate electrodes through the electrically conductive grid using at least one conductive contact to the electrically conductive grid formed through the second dielectric.

RF transistor amplifiers include an RF transistor amplifier die having a semiconductor layer structure, a coupling element on an upper surface of the semiconductor layer structure, and an interconnect structure on an upper surface of the coupling element so that the RF transistor amplifier die and the interconnect structure are in a stacked arrangement. The coupling element includes a first shielded transmission line structure.

A semiconductor device according to an embodiment includes: a first trench and a second trench extending in a first direction; a first gate electrode in the first trench; a second gate electrode in the second trench; a first gate wire including a first portion extending in a second direction perpendicular to the first direction and a third portion extending in the second direction; a second gate wire including a first portion extending in the second direction and a third portion extending in the second direction; a first gate electrode pad; and a second gate electrode pad. The first portion of the second gate wire is between the first portion and the third portion of the first gate wire, and the third portion of the first gate wire is between the first portion and the third portion of the second gate wire.

The present invention relates to a high-frequency semiconductor device. A conventional high-frequency semiconductor device including an input second-order harmonic matching circuit has such a problem that gain decrease occurs. In a high-frequency semiconductor device (100) of the present invention, two adjacent unit transistor cells (7) and (8) are connected to one input second-order harmonic matching circuit (19) provided on an upper surface of a semiconductor substrate (1). The input second-order harmonic matching circuit (19) includes a first capacitor (13), a first inductor (14), a second capacitor (15), and a second inductor (16). The first capacitor (13) and the first inductor (14) resonate at the frequency of a fundamental wave, and each of impedances as seen by input electrodes of the two unit transistor cells (7) and (8) is short-circuited at the frequency of a second-order harmonic.

A semiconductor device is provided with circuit patterns and dummy patterns. The circuit patterns facilitate circuit operations and the dummy patterns do not facilitate circuit operations. The dummy patterns are formed as patterns at which crystal defects are more likely to be caused by stress than the circuit patterns.