A power transistor die includes a semiconductor die with input and output die sides, and a transistor integrally formed in the semiconductor die between the input die side and the output die side, where the transistor has an input and an output (e.g., a gate and a drain, respectively). The power transistor die also includes an input bondpad and a first output bondpad integrally formed in the semiconductor die between the input die side and the transistor. The input bondpad is electrically connected to the input of the transistor. A conductive structure directly electrically connects the output of the transistor to the first output bondpad. A second output bondpad, which also may be directly electrically connected to the transistor output, may be integrally formed in the semiconductor die between the transistor and the output die side.

A semiconductor device includes a gate electrode, first and second transistors arranged in a first direction, first and second drain wirings each connected to a corresponding drain region of the first and second transistors, first output wiring extending in a second direction orthogonal to the first direction and having one end connected to a portion adjacent to the second transistor of the first drain wiring, second output wiring extending in the second direction and having one end connected to a portion adjacent to the first transistor of the second drain wiring, third output wiring extending in the first direction and connected to the other end of the first output wiring and the other end of the second output wiring, and fourth output wiring connecting a center portion of the third output wiring to an output terminal.

A semiconductor device includes an integrated circuit that is disposed at a first face side of a semiconductor substrate, the semiconductor substrate having a first face and a second face, the second face opposing the first face, the semiconductor substrate having a through hole from the first face to the second face; an external connection terminal that is disposed at the first face side; a conductive portion that is disposed in the through hole, the conductive portion being electrically connected to the external connection terminal; and an electronic element that is disposed at a second face side.

An electronic circuit is disclosed. The electronic circuit includes a distributed power switch. In some embodiments, the electronic circuit also includes one or more of a distributed gate driver, a distributed gate pulldown device, a distributed diode, and a low resistance gate and/or source connection structure. An electronic component comprising the circuit, and methods of manufacturing the circuit are also disclosed.

In some embodiments, a semiconductor device includes a semiconductor die including a vertical transistor device having a source electrode, a drain electrode and a gate electrode, the semiconductor die having a first surface and a metallization structure. The metallization structure includes a first conductive layer above the first surface, a first insulating layer above the first conductive layer, a second conductive layer above the first insulating layer, a second insulating layer above the second conductive layer and a third conductive layer above the second insulting layer. The third conductive layer includes at least one source pad electrically coupled to the source electrode, at least one drain pad electrically coupled to the drain electrode and at least one gate pad electrically coupled to the gate electrode.

In a semiconductor device including gate fingers each having a linear shape extending from a feed line, and arranged in areas between drain electrodes and source electrodes, open stubs are connected directly to the feed line.

According to one embodiment, a semiconductor device includes: a semiconductor layer including a first plane extending along a plane including a first axis and a second axis; a first electrode extending along the first axis; a second electrode extending along the second axis; and a third electrode above the first plane. The third electrode is electrically coupled to the first electrode and the second electrode, and includes a first portion, a second portion and a third portion. The first portion crosses the first electrode. The second portion crosses the second electrode. The third portion crosses the second electrode and is separate at a first end from the second portion.

In an example, a silicon carbide device includes a silicon carbide body. The silicon carbide body includes a central region and a peripheral region surrounding the central region. The central region includes a source region of a first conductivity type. The peripheral region includes a doped region of a second conductivity type. A stripe-shaped gate electrode extends through the central region and into the peripheral region. A contiguous source metallization is formed on the central region and on an inner portion of the peripheral region. The contiguous source metallization and the source region form a first ohmic contact in the central region. The contiguous source metallization and the doped region form a second ohmic contact in the peripheral region.

A semiconductor device includes a die body having a frontside and a transistor having an active area formed in the die body, the active area being bounded by an outer periphery. An interconnect structure is formed over the frontside of the die body and contains patterned electrically conductive material defining first, second, and third contacts electrically coupled to first, second, and third subregions, respectively, within the active area of the transistor. A frontside input/output (I/O) interface is formed in an outer portion of the interconnect structure. The frontside I/O interface contains first, second, and third contact pads, the first contact pad being electrically connected to the first contact, the second contact pad being electrically connected to the second contact, and the third contact pad being electrically connected the third contact, wherein the third contact pad is positioned at a location overlying the active area of the transistor.

An amplifier module includes a module substrate and first and second power transistor dies. The first power transistor die is coupled to a mounting surface of the module substrate, and has first and second input/output (I/O) contact pads and a first ground contact pad, all of which are all exposed at a surface of the first power transistor die that faces toward the mounting surface of the module substrate. The second power transistor die also is coupled to the mounting surface, and has third and fourth I/O contact pads and a second ground contact pad. The third and fourth I/O contact pads are exposed at a surface of the second power transistor die that faces away from the mounting surface of the module substrate, and the second ground contact pad is exposed at a surface of the second power transistor die that faces toward the mounting surface.