A transistor amplifier includes a semiconductor layer structure comprising first and second major surfaces and a plurality of unit cell transistors on the first major surface that are electrically connected in parallel, each unit cell transistor comprising a gate finger coupled to a gate manifold, a drain finger coupled to a drain manifold, and a source finger. The semiconductor layer structure is free of a via to the source fingers on the second major surface.

A semiconductor device of the present invention includes a semiconductor layer including a main IGBT cell and a sense IGBT cell connected in parallel to each other, a first resistance portion having a first resistance value formed using a gate wiring portion of the sense IGBT cell and a second resistance portion having a second resistance value higher than the first resistance value, a gate wiring electrically connected through mutually different channels to the first resistance portion and the second resistance portion, a first diode provided between the gate wiring and the first resistance portion, a second diode provided between the gate wiring and the second resistance portion in a manner oriented reversely to the first diode, an emitter electrode disposed on the semiconductor layer, electrically connected to an emitter of the main IGBT cell, and a sense emitter electrode disposed on the semiconductor layer, electrically connected to an emitter of the sense IGBT cell.

The fabrication of field-effect transistor (FET) devices is described herein where the FET devices include one or more body contacts implemented between source, gate, drain (S/G/D) assemblies to improve the influence of a voltage applied at the body contact on the S/G/D assemblies. The FET devices can include source fingers and drain fingers interleaved with gate fingers. The source and drain fingers of a first S/G/D assembly can be electrically connected to the source and drain fingers of a second S/G/D assembly. The source fingers and the drain fingers can be arranged in alternating rows.

The present invention discloses a modularized circuit for isolated circuit, wherein the isolated circuit includes at least two circuit components connecting in parallel and/or series, the circuit components, according to a circuit connection configuration, weld corresponding pins of the components directly, forming an integrated module in accordance with a desired connection method of the circuit, and saving circuit boards and wires; the circuit components are designed as a parallelepiped, and a plurality of bonding pads are arranged on part of an area on a surface of the parallelepiped. Due to constructing a circuit unit by welding connections in a way of building blocks, welding directly between components in a 3D space, comparing to the circuits limited in a circuit board plane as a PCB, it owns a wider design space.

An SiC semiconductor device includes an SiC semiconductor layer including an SiC monocrystal and having a first main surface as a device surface, a second main surface at a side opposite to the first main surface, and a side surface connecting the first main surface and the second main surface, a main surface insulating layer including an insulating material, covering the first main surface of the SiC semiconductor layer, and having an insulating side surface continuous to the side surface of the SiC semiconductor layer, and a boundary modified layer including a first region that is modified to be of a property differing from the SiC monocrystal and a second region that is modified to be of a property differing from the insulating material, and being formed across the side surface of the SiC semiconductor layer and the insulating side surface of the main surface insulating layer.

A metal wiring method for reducing gate resistance of a narrow control gate structure, wherein the gate structure is etched with first gate electrodes and second gate electrodes at regular intervals and kept with complete gate electrodes at regular intervals, thereby constituting a structure in which the first and second gate electrodes and the complete gate electrodes are spaced apart. A first contact hole is etched on the complete gate electrode to draw out metal as a first metal layer. A second contact hole is etched on a source region and a split gate to draw out metal as a second metal layer. These two metal layers are separated by a dielectric layer. A multi-point contact of the first layer of metal with the gate electrode in a Y direction reduces the gate resistance caused by an excessively long path in the Y direction of a control gate electrode.

A multi-finger transistor including plural control electrodes (2), plural first electrodes (3), and plural second electrodes (4) is provided on a semiconductor substrate (1). A resin film (14,15) covers the transistor. A first wiring (8) electrically connecting the plural first electrodes (3) to one other is provided on the resin film (14,15). The resin film (14,15) covers contact portions between the first wiring (8) and the plural first electrodes (3). A first hollow structure (16) sealed with the resin film (14,15) is provided around the plural control electrodes (2) and the plural second electrodes (4).

Representative techniques and devices including process steps may be employed to mitigate the potential for delamination of bonded microelectronic substrates due to metal expansion at a bonding interface. For example, a metal pad may be disposed at a bonding surface of at least one of the microelectronic substrates, where the contact pad is positioned offset relative to a TSV in the substrate and electrically coupled to the TSV.

The wiring length of MOS transistors is shortened. A source region has both ends made smaller in width than a central part. A first channel region and a second channel region are adjacent to corresponding outer peripheral parts. A first drain region and a second drain region are adjacent to the first channel region and the second channel region, respectively. Gate electrodes are on respective surfaces of the first channel region and the second channel region through an insulating film, joined to each other, and connected to a gate wire. Drain electrodes are placed on the respective surfaces of the first drain region and the second drain region and joined to each other near a second end and connected to a drain wire. At least one of the gate wire or the drain wire is smaller in width than the central part of the source region.

An SiC semiconductor device includes an SiC semiconductor layer including an SiC monocrystal that is constituted of a hexagonal crystal and having a first main surface as a device surface facing a c-plane of the SiC monocrystal and has an off angle inclined with respect to the c-plane, a second main surface at a side opposite to the first main surface, and a side surface facing an a-plane of the SiC monocrystal and has an angle less than the off angle with respect to a normal to the first main surface when the normal is 0°.