A Field Effect Transistor (FET) capable of operating at high frequencies and includes comb-shaped source and drain electrodes. The comb-shaped drain electrode includes a plurality of thin comb-shape drain electrode layers at corresponding levels of the FET, each comb-shaped drain electrode layer including a plurality of drain electrode fingers having substantially the same width as the comb-shaped drain electrodes of each other layer. The comb-shaped source electrode includes a plurality of comb-shape source electrode layers at the corresponding levels, each comb-shaped drain electrode layer including a plurality of drain electrode fingers having substantially the same width as the comb-shaped source electrodes of each other layer. In addition, the inter-level retraction of adjacent drain electrode layers is the same or substantially the same. Similarly, the inter-level retraction of adjacent source electrode layers is the same or substantially the same.

A transistor device includes a field plate that extends from a source runner layer and/or a source contact layer. The field plate can be coplanar with and/or below a gate runner layer. The gate runner layer is routed away from a region directly above the gate metal layer by a gate bridge, such that the field plate can extend directly above the gate metal layer without being interfered by the gate runner layer. Coplanar with the source runner layer or the source contact layer, the field plate is positioned close to the channel region, which helps reduce its parasitic capacitance. By vertically overlapping the metal gate layer and the field plate, the disclosed HEMT device may achieve significant size efficiency without additional routings.

A silicon carbide semiconductor device includes an upper gate electrode including a gate pad and a gate wiring line, and an upper source electrode including first and second source pads. The gate wiring line includes a gate global wiring line extending to encircle the source pads, and a gate connection wiring line. The upper source electrode includes an outer periphery source wiring line extending to encircle the gate global wiring line, and first and second source connections connecting the outer periphery source wiring line to the first and second source pads, respectively. The gate global wiring line includes a first portion, a second portion, and a third portion. The first portion is split at a first substrate corner and a second substrate corner and lies between the first substrate corner and the second substrate corner.splitsplit

According to one embodiment, a display device, includes a first substrate including a first conductive layer, a second substrate including a base having a first upper surface on a side opposite to a first lower surface opposed to the first substrate, a second conductive layer provided on the first upper surface, a third conductive layer provided on the first upper surface and electrically connected to the second conductive layer, a fourth conductive layer covering the third conductive layer and having a light-shielding property, a first through hole provided in the base, and an insulating material overlapping the connection material and having a light-shielding property.

A second protective film is formed by applying high-viscosity resin by an inkjet method, in two patterns that extend parallel to and along a boundary between a first protective film and a plating film, the boundary being sandwiched between the two patterns. A low-viscosity resin is applied between these first and second patterns of the second protective film by the inkjet method. The low-viscosity resin has a viscosity that is lower than that of the high-viscosity resin for forming the second protective film, and a fluidity that is higher than that of the high-viscosity resin and thus, leaks and spreads into a gap between the first protective film and the plating film. The third protective film adheres to the first and second patterns, is formed across the boundary between the first protective film and the plating film, and is embedded in the gap whereby the gap is plugged.

Provided is a package structure including a substrate, a metal pad, a first polymer layer, a second polymer layer, a redistribution layer (RDL), and a third polymer layer. The metal pad is located on the substrate. The first polymer layer is located on the substrate. The first polymer layer has a first opening which exposes a portion of a top surface of the metal pad. The second polymer layer is located on the first polymer layer. The second polymer layer has a second opening which exposes the portion of the top surface of the metal pad and a first top surface of the first polymer layer. The RDL covers the portion of the top surface of the metal pad and extends onto a portion of the first top surface of the first polymer layer and the second polymer layer. The third polymer layer is located on the RDL.

A semiconductor device includes an integrated circuit that is disposed at a first face side of a semiconductor substrate, the semiconductor substrate having a first face and a second face, the second face opposing the first face, the semiconductor substrate having a through hole from the first face to the second face; an external connection terminal that is disposed at the first face side; a conductive portion that is disposed in the through hole, the conductive portion being electrically connected to the external connection terminal; and an electronic element that is disposed at a second face side.

A semiconductor device is provided with one or more gate fingers (20) that are provided in an active region on a semiconductor substrate (1), and a source finger (30) and a drain finger (40) that are provided in the active region and arranged alternately to allow each gate finger to be sandwiched between the source and drain fingers. The semiconductor device includes terminal circuit (60) that has inductive impedance at the frequency of a signal input to an input terminal of the one or more gate fingers, and is directly or indirectly connected to the one or more gate fingers at an area being spaced away from a connecting position of the input terminal (21a) of the one or more gate fingers (20).

A compound semiconductor device includes a heterojunction bipolar transistor and a bump. The heterojunction bipolar transistor includes a plurality of unit transistors. The bump is electrically connected to emitters of the plurality of unit transistors. The plurality of unit transistors are arranged in a first direction. The bump is disposed above the emitters of the plurality of unit transistors while extending in the first direction. The emitter of at least one of the plurality of unit transistors is displaced from a center line of the bump in the first direction toward a first side of a second direction which is perpendicular to the first direction. The emitter of at least another one of the plurality of unit transistors is displaced from the center line of the bump in the first direction toward a second side of the second direction.

High power transistors, such as high power gallium nitride (GaN) transistors, are described. These high power transistors have larger total gate widths than conventional high power transistors by arranging multiple linear arrays of gate, drain, and source contacts in parallel. Thereby, the total gate width and the power rating of the high power transistor may be increased without elongating the die of the high power transistor. Accordingly, the die of the high power transistor may be mounted in a smaller circuit package relative to conventional dies with the same power rating.