Devices and methods are described for fabricating field effect transistors (FET) using compound semiconductor front end of line (FEOL) integrated with back end of line (BEOL) technologies for applications including power management and communications. Wafer-level FEOL processing with a minimum number of thin interconnects may be used to produce multiple chiplets, which are small, high current density functional building blocks. Chiplets may have tight source/drain finger pitch, high gate width per area, and minimum lateral current flow, to reduce resistance, FEOL process complexity, and cost. Panel-level BEOL processing may serve as an inexpensive extension of FEOL processes. BEOL may form multiple interconnect layers and via bars with progressively increasing thickness and cross section area. These BEOL interconnects and via bars connect together the parallel chiplets, handle lateral flow of high current and reduce electrical and thermal resistance the FETs to increase current carrying capacity of the FETs.

A short-channel metal oxide semiconductor varactor may include a source region of a first polarity having a source via contact. The varactor may further include a drain region of the first polarity having a drain via contact. The varactor may further include a channel region of the first polarity between the source region and the drain region. The channel region may include a gate. The varactor may further include at least one self-aligned contact (SAC) on the gate and between the source via contact and the drain via contact.

A semiconductor structure includes a plurality of source/drain regions, a plurality of channel/body regions located between the source/drain regions, and a polysilicon gate structure located over the plurality of channel/body regions. The polysilicon gate structure includes a plurality of polysilicon gate fingers, each extending over a corresponding one of the channel/body regions. Each polysilicon gate finger includes first and second rectangular portions that extend in parallel with a first axis, and a connector portion that introduces an offset between the first and second rectangular portions along the first axis. This offset results in each source/drain region having a first section with a first length, and a second section with a second length, greater than the first length. A single column of contacts are provided in the first section of each source/drain region, and multiple columns of contacts are provided in the second section of each source/drain region.

A Field Effect Transistor (FET) capable of operating at high frequencies and includes comb-shaped source and drain electrodes. The comb-shaped drain electrode includes a plurality of thin comb-shape drain electrode layers at corresponding levels of the FET, each comb-shaped drain electrode layer including a plurality of drain electrode fingers having substantially the same width as the comb-shaped drain electrodes of each other layer. The comb-shaped source electrode includes a plurality of comb-shape source electrode layers at the corresponding levels, each comb-shaped drain electrode layer including a plurality of drain electrode fingers having substantially the same width as the comb-shaped source electrodes of each other layer. In addition, the inter-level retraction of adjacent drain electrode layers is the same or substantially the same. Similarly, the inter-level retraction of adjacent source electrode layers is the same or substantially the same.

A semiconductor device includes an integrated circuit that is disposed at a first face side of a semiconductor substrate, the semiconductor substrate having a first face and a second face, the second face opposing the first face, the semiconductor substrate having a through hole from the first face to the second face; an external connection terminal that is disposed at the first face side; a conductive portion that is disposed in the through hole, the conductive portion being electrically connected to the external connection terminal; and an electronic element that is disposed at a second face side.

A semiconductor device comprises: a substrate; a multi-layer semiconductor layer located on the substrate, the multi-layer semiconductor layer being divided into an active area and a passive area outside the active area; a gate electrode, a source electrode and a drain electrode all located on the multi-layer semiconductor layer and within the active area; and a heat dissipation layer covering at least one portion of the active area and containing a heat dissipation material. In embodiments of the present invention, a heat dissipation layer covering at least one portion of the active area is provided in the semiconductor device. The arrangement of the heat dissipation layer adds a heat dissipation approach for the semiconductor device in the planar direction, thus the heat dissipation effect of the semiconductor device is improved.

Disconnection of a base line is suppressed even when a short-side direction of a collector layer is parallel to crystal orientation [011]. A bipolar transistor includes: a collector layer that has a long-side direction and a short-side direction in a plan view, in which the short-side direction is parallel to crystal orientation [011], a cross-section perpendicular to the short-side direction has an inverted mesa shape, and a cross-section perpendicular to the long-side direction has a forward mesa shape; a base layer that is formed on the collector layer; a base electrode that is formed on the base layer; and a base line that is connected to the base electrode and that is drawn out from an end in the short-side direction of the collector layer to the outside of the collector layer in a plan view.

Performance of a semiconductor device is improved without increasing an area size of a semiconductor chip. For example, a source electrode of a power transistor and an upper electrode of a capacitor element have an overlapping portion. In other word, the upper electrode of the capacitor element is formed over the source electrode of the power transistor through a capacitor insulating film. That is, the power transistor and the capacitor element are arranged in a laminated manner in a thickness direction of the semiconductor chip. As a result, it becomes possible to add a capacitor element to be electrically coupled to the power transistor while suppressing an increase in planar size of the semiconductor chip.

An integrated circuit is provided and includes multiple first conductive segments, multiple second conductive segments, multiple third conductive segments, multiple fourth conductive segments, a first conductive line, and a second conductive line. The plurality of first conductive segments and the third conductive segments are arranged between multiple first gates, and the second conductive segments and the fourth conductive segments are arranged between multiple second gates. The first conductive line transmits a drain/source signal and is coupled to the first conductive segments and the second conductive segments. The second conductive line transmits a source/drain signal and is coupled to the third conductive segments and the fourth conductive segments. The plurality of third conductive segments and the fourth conductive segments are mirrored symmetrically with respect to the second conductive line in a plan view.

A Doherty amplifier includes a substrate, a first transistor provided on the substrate and including first gate electrodes, first drain electrodes, a first gate bus bar and a first drain bus bar, a second transistor provided on the substrate and including second gate electrodes, second drain electrodes, a second gate bus bar having a first end, and a second drain bus bar, a combining node provided on the substrate and combining a first signal amplified by the first transistor and a second signal amplified by the second transistor, a first line provided on the substrate and connecting the first drain bus bar and the combining node, and a second line provided on the substrate, connecting the second drain bus bar and the combining node, and connected to a second end of the second drain bus bar located diagonally across the second transistor with respect to the first end.