A UV LED package disclosed herein includes a submount, a UV LED chip adapted to emit UV light at 200 nm to 400 nm, and a package body mounted with the submount. The submount includes a heat dissipating substrate, a first reflective electrode film and a second reflective electrode film separated from each other by an electrode separation gap on the heat dissipating substrate, a first flip-chip bonding pad and a first wire bonding pad disposed on the first reflective electrode film, and a second flip-chip bonding pad and a second wire bonding pad disposed on the second reflective electrode film. The UV LED chip includes a first conductive electrode pad corresponding to the first flip-chip bonding pad and a second conductive electrode pad corresponding to the second flip-chip bonding pad. The UV LED chip is flip-chip bonded to the submount through a first bonding bump interposed between the first flip-chip bonding pad and the first conductive electrode pad and a second bonding bump interposed between the second flip-chip bonding pad and the second conductive electrode pad. The package body includes a first metal body electrically connected to the first wire bonding pad through a first bonding wire and a second metal body separated from the first metal body by an insulating material and electrically connected to the second wire bonding pad through a second bonding wire.

In a MOSFET, the lead parts of gate lead wiring that lead out a gate electrode on the periphery of a substrate constitute a non-operative region where it is impossible to dispose a MOSFET transistor cell (C) that will function as efficiently as inside an element region. If the gate lead wiring is disposed along the four edges of a chip, for example, the area of the non-operative region increases, limiting the extent to which the surface area of the element region can be enlarged and the chip surface area reduced. In the present invention, gate lead wiring and a conductor, which is connected to the gate lead wiring and a protection diode, are disposed in a non-curved, linear configuration along one edge of a chip. In addition, a first gate electrode layer that extends superimposed on the gate lead wiring and the conductor, and connects the gate lead wiring and the conductor to the protection diode, has no more than one curved part. Furthermore, the protection diode is disposed adjacent to the conductor or the gate lead wiring, and a portion of the protection diode is disposed near a gate pad.

According to one embodiment, an electrostatic discharge semiconductor device includes one or more wiring layers first disposed over a substrate, including: a wiring electrically connected at a first connecting point of a pad, a second wiring electrically connected at a second connecting point of a ground wiring, and a third wiring electrically connected at a third connecting point of the ground wiring; a first transistor formed in the substrate comprising a first diffusion region electrically connected to the first wiring, a second diffusion region electrically connected to the second wiring, and a gate electrically connected to the ground wiring; and a second transistor formed in the substrate comprising the first diffusion region electrically connected to the first wiring, a third diffusion region electrically connected to the third wiring, and a gate electrically connected to the ground wiring, wherein, a first resistance value of a first current pathway leading from the first connecting point to the second connecting point via the first transistor is different from a second resistance value of a second current pathway leading from the first connecting point to the third connecting point via the second transistor.

A multifinger transistor in which source fingers (201 to 206) and drain fingers (301 to 305) are arranged alternately with each of gate fingers (101 to 110) being sandwiched between one of the source fingers and one of the drain fingers is used. Line (10) and line (20) are attached to the source fingers (201 to 206) in an area on a gate side and causing a phase rotation such that the nearer to a central part a gate finger is, the more inductive the gate finger is.

A semiconductor package includes a substrate and a flip-chip on the substrate The flip-chip includes first bump pads and second bump pads on an active surface of the flip-chip. Vias are disposed on the second bump pads. The first bump pads have a pad size that is smaller than that of the second bump pads. An underfill layer is disposed between the flip-chip and the substrate to surround the vias. The underfill layer is in direct contact with a surface of each of the first bump pads.

A semiconductor device according to an embodiment includes: a substrate having a first plane and a second plane provided on the opposite side of the first plane; a first nitride semiconductor layer provided on the first plane; source electrodes provided on the first nitride semiconductor layer; drain electrodes provided on the first nitride semiconductor layer, each of the drain electrodes provided between the source electrodes; gate electrodes provided on the first nitride semiconductor layer, each of the gate electrodes provided between each of the source electrodes and each of the drain electrodes; a first wire provided on the second plane and electrically connected to the source electrodes; a second wire electrically connected to the drain electrodes; a third wire provided on the second plane and electrically connected to the gate electrodes; and an insulating interlayer provided between the first nitride semiconductor layer and the second wire.

A semiconductor device includes an integrated circuit that is disposed at a first face side of a semiconductor substrate, the semiconductor substrate having a first face and a second face, the second face opposing the first face, the semiconductor substrate having a through hole from the first face to the second face; an external connection terminal that is disposed at the first face side; a conductive portion that is disposed in the through hole, the conductive portion being electrically connected to the external connection terminal; and an electronic element that is disposed at a second face side.

A semiconductor device includes an integrated circuit that is disposed at a first face side of a semiconductor substrate, the semiconductor substrate having a first face and a second face, the second face opposing the first face, the semiconductor substrate having a through hole from the first face to the second face; an external connection terminal that is disposed at the first face side; a conductive portion that is disposed in the through hole, the conductive portion being electrically connected to the external connection terminal; and an electronic element that is disposed at a second face side.

A semiconductor device includes an integrated circuit that is disposed at a first face side of a semiconductor substrate, the semiconductor substrate having a first face and a second face, the second face opposing the first face, the semiconductor substrate having a through hole from the first face to the second face; an external connection terminal that is disposed at the first face side; a conductive portion that is disposed in the through hole, the conductive portion being electrically connected to the external connection terminal; and an electronic element that is disposed at a second face side.

A chip structure including a chip and a redistribution layer is provided. The chip includes a plurality of pads. The redistribution layer includes a dielectric layer and a plurality of conductive traces. The dielectric layer is disposed on the chip and has a plurality of contact windows located above the pads. The conductive traces are located on the dielectric layer and are electrically coupled to the pads through the contact windows. At least one of the conductive traces includes a body and at least one protrusion coupled to the body, and the at least one protrusion is coupled to an area of the body other than where the contact windows are coupled to on the body.