A semiconductor device comprising a switch and a method of making the same. The device, has a layout having one or more rectangular unit cells. Each unit cell includes a gate having a substantially cross-shaped part comprising four arms that divide the unit cell into quadrants; and a substantially loop-shaped part, wherein a center of the cross-shaped part is located inside the loop-shaped part, and wherein the loop-shaped part intersects each arm of the cross-shaped part to divide each quadrant into an inner region located inside the loop-shaped part; and an outer region located outside the loop-shaped part. Each unit cell also includes a substantially loop-shaped active region forming a source and drain of the switch. Each unit cell further includes a plurality of connection members extending over the gate, source and drain for providing electrical connections to the source and drain.

A CMOS device with a plurality of PMOS transistors and a plurality of NMOS transistors includes a first interconnect and a second interconnect on an interconnect level connecting a first subset and a second subset of PMOS drains together, respectively. The first and second subsets are different and the first and second interconnect are disconnected on the interconnect level. A third interconnect and a fourth interconnect on the interconnect level connect a first subset and a second subset of the NMOS drains together, respectively. The third interconnect and the fourth interconnect are disconnected on the interconnect level. The first, second, third, fourth interconnects are coupled together through at least one other interconnect level. Additional interconnects on the interconnect level connect the first and third interconnects together, and the second and fourth interconnects together, to provide parallel current paths with a current path through the at least one other interconnect level.

A semiconductor device includes a semiconductor substrate, a conductive pad over the semiconductor substrate, a conductor over the conductive pad, a polymeric material over the semiconductor substrate and surrounding the conductor, and a seed layer between the polymeric material and the conductor. A top surface of the conductor, a top surface of the polymeric material and a top surface of the seed layer are substantially coplanar.

A source interconnect and a drain interconnect are alternately provided between a plurality of transistor units. One bonding wire is connected to a source interconnect at a plurality of points. The other bonding wire is connected to a source interconnect at a plurality of points. In addition, one bonding wire is connected to a drain interconnect at a plurality of points. In addition, the other bonding wire is connected to a drain interconnect at a plurality of points.

An electronic component made up of field-effect transistor (FET) cells is disclosed. Each FET cell includes a finger region having drain, gate, and source fingers disposed over a semiconductor substrate. An isolation region extends across a first end of the finger region. An off-state linearization region abuts the first end of the isolation region. A doped well is disposed within the off-state linearization region over the semiconductor substrate. A dielectric layer is disposed over the doped region. A first conductive stripe is disposed over the dielectric layer in longitudinal alignment with the drain finger. A second conductive stripe is disposed over the dielectric layer in longitudinal alignment with the drain finger. A drain finger electrode is aligned over and coupled to both the drain finger and the first conductive stripe. A source finger electrode is aligned over and coupled to both the source finger and the second conductive stripe.

A second protective film is formed by applying high-viscosity resin by an inkjet method, in two patterns that extend parallel to and along a boundary between a first protective film and a plating film, the boundary being sandwiched between the two patterns. A low-viscosity resin is applied between these first and second patterns of the second protective film by the inkjet method. The low-viscosity resin has a viscosity that is lower than that of the high-viscosity resin for forming the second protective film, and a fluidity that is higher than that of the high-viscosity resin and thus, leaks and spreads into a gap between the first protective film and the plating film. The third protective film adheres to the first and second patterns, is formed across the boundary between the first protective film and the plating film, and is embedded in the gap whereby the gap is plugged.

A transistor device includes a field plate that extends from a source runner layer and/or a source contact layer. The field plate can be coplanar with and/or below a gate runner layer. The gate runner layer is routed away from a region directly above the gate metal layer by a gate bridge, such that the field plate can extend directly above the gate metal layer without being interfered by the gate runner layer. Coplanar with the source runner layer or the source contact layer, the field plate is positioned close to the channel region, which helps reduce its parasitic capacitance. By vertically overlapping the metal gate layer and the field plate, the disclosed HEMT device may achieve significant size efficiency without additional routings.

A semiconductor device may include an insulating layer, a pad, a circuit, at least one first wiring, at least-one second wiring, at least one third wiring, and a pad contact. The pad may be disposed on the insulating layer. The circuit may be disposed in the insulating layer. The circuit may be positioned below the pad. The first wiring may be disposed between the pad and the circuit. The second wiring may be disposed between the pad and the first wiring. The third wiring may be disposed between the pad and the second wiring. The pad contact may be configured to directly connect the pad to the circuit.

A process of forming a semiconductor device that includes an interconnection formed by electro-plating is disclosed. The process comprises steps of: forming a stopper layer on a first insulating film; covering the stopper layer and the first insulating film with a second insulating film; preparing a first mask having an edge that overlaps with the stopper layer; depositing a seed layer on the first mask and the second insulating film that is exposed from the first mask; preparing a second mask having an edge that overlaps with the stopper layer, the edge of the first mask being retreated from the edge of the second mask; forming an upper layer on the seed layer by electro-plating a metal so as not to overlap with the first mask; and removing the seed layer exposed from the upper layer by etching.

An LED module includes: a substrate having a main surface and a back surface which face in opposite directions from each other in a thickness direction; a first LED chip including a first electrode pad bonded to a surface facing the same direction as the main surface; a first wire having one end bonded to the first electrode pad; and a wiring pattern having a main surface electrode formed in the main surface, wherein the main surface electrode includes a first die pad portion which supports the first LED chip, and when viewed from the thickness direction, the first die pad portion includes a main pad portion to which the first LED chip is bonded and an auxiliary pad portion which protrudes from the main pad portion in a direction toward a position of the first electrode pad from the center position in the first LED chip.