A stacked field-effect transistor (FET) switch is disclosed. The stacked FET switch has a first FET device stack that is operable in an on-state and in an off-state and is made up of a first plurality of FET devices coupled in series between a first port and a second port, wherein the first FET device stack has a conductance that decreases with increasing voltage between the first port and the second port. The stacked FET switch also includes a second FET device stack that is operable in the on-state and in the off-state and is made up of a second plurality of FET devices coupled in series between the first port and the second port, wherein the second FET device stack has a conductance that increases with increasing voltage between the first port and the second port.

A semiconductor device that outputs a radio-frequency (RF) signal with high power is disclosed. The semiconductor device includes a housing, a semiconductor chip, an impedance converter, a capacitor, and a bonding wire. The housing includes a heat sink, an output lead terminal, and a bias terminal electrically isolated from the output lead terminal. The semiconductor chip is mounted on the heat sink of the housing. The impedance converter provides an input port, an output port, and an intermediate port between the input port and the output port thereof. The capacitor is mounted on the heat sink and between the impedance converter and the output lead terminal. The bonding wire connects the bias lead terminal with the intermediate port.

A semiconductor chip having a pad, a protective element, and an internal circuit for providing a semiconductor chip having a protective circuit with high noise resistance, wherein the semiconductor chip is characterized in that the resistance value of metal wiring on a path reaching the pad and the protective element is higher than the resistance value of the protective element.

A semiconductor device of the present invention includes a semiconductor layer including a main IGBT cell and a sense IGBT cell connected in parallel to each other, a first resistance portion having a first resistance value formed using a gate wiring portion of the sense IGBT cell and a second resistance portion having a second resistance value higher than the first resistance value, a gate wiring electrically connected through mutually different channels to the first resistance portion and the second resistance portion, a first diode provided between the gate wiring and the first resistance portion, a second diode provided between the gate wiring and the second resistance portion in a manner oriented reversely to the first diode, an emitter electrode disposed on the semiconductor layer, electrically connected to an emitter of the main IGBT cell, and a sense emitter electrode disposed on the semiconductor layer, electrically connected to an emitter of the sense IGBT cell.

A semiconductor device includes a semiconductor layer having an element formation region in which a semiconductor element is formed. An element isolation well is formed in a surface portion of the semiconductor layer to isolate the element formation region. A field insulating film is formed on a surface of the semiconductor layer. The field insulating film surrounds the element formation region in an annular shape when viewed from a top. An interlayer insulating film is formed on the semiconductor layer. A wiring is formed on the interlayer insulating film. A conductive film is formed on the field insulating film.

The present invention provides a semiconductor device that can reduce effects of noise without complicating processes or increasing chip area.

The semiconductor device according to an aspect of the present invention includes a semiconductor substrate, a drain region, a drift region, a base region, a source region, a gate electrode, an interlayer insulating film, a conductive layer electrically coupled to the drain region, a wiring line, and a contact plug electrically coupled to the source region and the wiring line. The interlayer insulating film has an intermediate interlayer insulating film. The intermediate interlayer insulating film is arranged between the conductive layer and the contact plug. The intermediate interlayer insulating film is a thermal oxide film of a material that forms the conductive layer.

A CMOS device with a plurality of PMOS transistors each having a PMOS drain and a plurality of NMOS transistors each having an NMOS drain includes a first interconnect on an interconnect level extending in a length direction to connect the PMOS drains together. A second interconnect on the interconnect level extends in the length direction to connect the NMOS drains together. A set of interconnects on at least one additional interconnect level couple the first interconnect and the second interconnect together. A third interconnect on the interconnect level extends perpendicular to the length direction and is offset from the set of interconnects to connect the first interconnect and the second interconnect together.

A semiconductor device includes: diffusion layers that are formed over a semiconductor substrate in a first direction, that are separated from one another by separation regions, and that serve as drain regions or source regions of respective transistors; a gate electrode of the transistors, which is formed in the first direction so as to straddle the diffusion layers; gate extraction wirings that are formed above the separation regions so as to sandwich therebetween the individual diffusion layers in the first direction, that are electrically coupled to the gate electrode above the separation regions, and that supply a gate signal to the gate electrode.

An imaging component includes a laminated substrate formed of a resin material; a plurality of electrode pads disposed on an upper face of the laminated substrate, an imaging element being to be mounted on the plurality of electrode pads; and a plurality of conductor patterns which are belt-shaped and disposed between layers of the laminated substrate, the plurality of conductor patterns being connected to the plurality of electrode pads, respectively. A part of at least one of the plurality of conductor patterns has a widened portion, the widened portion being located immediately below any of electrode pads which are not connected to the at least one of the plurality of conductor patterns.

A semiconductor device is provided which realizes speed-up and cost reduction. The semiconductor device has a high side gate driver including a depression type FET and an enhancement type FET, a low side gate driver including a depression type FET and an enhancement type FET, and a high side power FET and a low side power FET as field-effect transistors, in which the high side gate driver, the low side gate driver, the high side power FET and the low side power FET are integrated in the same chip.