H01L23/4824

Encapsulated semiconductor device package with heatsink opening, and methods of manufacture thereof
09787254 · 2017-10-10 · ·

Embodiments include packaged semiconductor devices and methods of manufacturing packaged semiconductor devices. A semiconductor die includes a conductive feature coupled to a bottom surface of the die. The conductive feature only partially covers the bottom die surface to define a conductor-less region that spans a portion of the bottom die surface. The die is encapsulated by attaching the encapsulant material to the bottom die surface (e.g., including over the conductor-less region). The encapsulant material includes an opening that exposes the conductive feature. After encapsulating the die, a heatsink is positioned within the opening, and a surface of the heatsink is attached to the conductive feature. Because the heatsink is attached after encapsulating the die, the heatsink sidewalls are not directly bonded to the encapsulant material.

Transistor with bypassed gate structure field

A transistor device includes a source contact extending in a first direction, a gate finger extending in the first direction adjacent the source contact, and a drain contact adjacent the gate finger, wherein the gate finger is between the drain contact and the source contact. The device further includes a gate jumper extending in the first direction, a gate bus connected to the gate jumper and the gate finger, and a gate signal distribution bar that is spaced apart from the gate bus in the first direction and that connects the gate jumper to the gate finger.

BODY CONTACTS FOR FIELD-EFFECT TRANSISTORS

Field-effect transistor (FET) devices are described herein that include one or more body contacts implemented near source, gate, drain (S/G/D) assemblies to improve the influence of a voltage applied at the body contact on the S/G/D assemblies. For example, body contacts can be implemented between S/G/D assemblies rather than on the ends of such assemblies. This can advantageously improve body contact influence on the S/G/D assemblies while maintaining a targeted size for the FET device.

Lead frame for mounting LED elements, lead frame with resin, method for manufacturing semiconductor devices, and lead frame for mounting semiconductor elements

A lead frame for mounting LED elements includes a frame body region and a large number of package regions arranged in multiple rows and columns in the frame body region. The package regions each include a die pad on which an LED element is to be mounted and a lead section adjacent to the die pad, the package regions being further constructed to be interconnected via a dicing region. The die pad in one package region and the lead section in another package region upward or downward adjacent to the package region of interest are connected to each other by an inclined reinforcement piece positioned in the dicing region.

SEMICONDUCTOR DEVICE
20170271326 · 2017-09-21 ·

A semiconductor device includes a substrate, a plurality of transistors formed on a transistor region of the substrate, a plurality of diodes formed on a diode region of the substrate, the transistors and the diodes being arranged in a first direction, a first line formed over the substrate and extending between the transistors and the diodes, a plurality of first branch lines extending from the first line in the first direction to form a drain electrode of the transistors, and a plurality of second branch lines extending from the first line in the first direction to form an anode electrode of the diodes.

SEMICONDUCTOR PACKAGE
20170243814 · 2017-08-24 ·

A semiconductor package includes a substrate and a flip-chip on the substrate The flip-chip includes first bump pads and second bump pads on an active surface of the flip-chip. Vias are disposed on the second bump pads. The first bump pads have a pad size that is smaller than that of the second bump pads. An underfill layer is disposed between the flip-chip and the substrate to surround the vias. The underfill layer is in direct contact with a surface of each of the first bump pads.

SEMICONDUCTOR DEVICE INCLUDING SENSE INSULATED-GATE BIPOLAR TRANSISTOR
20170236916 · 2017-08-17 · ·

A semiconductor device of the present invention includes a semiconductor layer including a main IGBT cell and a sense IGBT cell connected in parallel to each other, a first resistance portion having a first resistance value formed using a gate wiring portion of the sense IGBT cell and a second resistance portion having a second resistance value higher than the first resistance value, a gate wiring electrically connected through mutually different channels to the first resistance portion and the second resistance portion, a first diode provided between the gate wiring and the first resistance portion, a second diode provided between the gate wiring and the second resistance portion in a manner oriented reversely to the first diode, an emitter electrode disposed on the semiconductor layer, electrically connected to an emitter of the main IGBT cell, and a sense emitter electrode disposed on the semiconductor layer, electrically connected to an emitter of the sense IGBT cell.

CHIP DIODE AND METHOD FOR MANUFACTURING SAME
20170222062 · 2017-08-03 · ·

The present invention is directed to a chip diode with a Zener voltage Vz of 4.0 V to 5.5 V, including a semiconductor substrate having a resistivity of 3 m.Math.cm to 5 m.Math.cm and a diffusion layer formed on a surface of the semiconductor substrate and defining a diode junction region with the semiconductor substrate therebetween, in which the diffusion layer has a depth of 0.01 m to 0.2 m from the surface of the semiconductor substrate.

Hybrid microwave integrated circuit
09721909 · 2017-08-01 · ·

A radio frequency (RF) integrated circuit includes a first layer of semiconductor material in which a high electron mobility transfer (HEMT) device is formed. A semiconductor heat spreader substrate supports the first layer of semiconductor material. A pair of matching circuits are electrically connected to the HEMT device, wherein the pair of matching circuits are supported on a semiconductor substrate of a semiconductor material different than the semiconductor material of the first semiconductor heat spreader substrate. The first layer of semiconductor material and the first semiconductor heat spreader substrate have a thickness that is less than a second thickness of the semiconductor substrate supporting the pair of matching circuits.

Parasitic channel mitigation via reaction with active species

III-nitride materials are generally described herein, including material structures comprising III-nitride material regions and silicon-containing substrates. Certain embodiments are related to gallium nitride materials and material structures comprising gallium nitride material regions and silicon-containing substrates.