A method for direct bonding an electronic chip onto a substrate or another electronic chip, the method including: carrying out a hydrophilic treatment of a portion of, a surface of the electronic chip and of a portion of a surface of the substrate or of the other electronic chip; depositing an aqueous fluid on the portion of the surface of the substrate or of the second electronic chip; depositing the portion of the surface of the electronic chip on the aqueous fluid; drying the aqueous fluid until the portion of the surface of the electronic chip is rigidly connected to the portion of the surface of the substrate or of the other electronic chip: and during at least part of the drying of the aqueous fluid, emitting ultrasound into the aqueous fluid through the substrate or the other electronic chip.

A method of manufacturing a semiconductor element according to the present disclosure includes an element forming step (S1) of forming, on an underlying substrate (11), a semiconductor element (15) connected to the underlying substrate (11) via a connecting portion (13b) and including an upper surface (15a) inclined with respect to a growth surface of the underlying substrate (11), a preparing step (S2) of preparing a support substrate (16) including an opposing surface (16c) facing the underlying substrate (11), a bonding step (S3) of pressing the upper surface (15a) of the semiconductor element (15) against the opposing surface (16c) of the support substrate (16) and heating the upper surface (15a) to bond the upper surface (15a) of the semiconductor element (15) to the support substrate (16), and a peeling step (S4) of peeling the semiconductor element (15) from the underlying substrate (11).

A package structure includes a first dielectric layer, semiconductor device(s) attached to the first dielectric layer, and an embedding material applied to the first dielectric layer so as to embed the semiconductor device therein, the embedding material comprising one or more additional dielectric layers. Vias are formed through the first dielectric layer to the at least one semiconductor device, with metal interconnects formed in the vias to form electrical interconnections to the semiconductor device. Input/output (I/O) connections are located on one end of the package structure on one or more outward facing surfaces thereof to provide a second level connection to an external circuit. The package structure interfits with a connector on the external circuit to mount the package perpendicular to the external circuit, with the I/O connections being electrically connected to the connector to form the second level connection to the external circuit.

A stacking structure including a first die, a second die stacked on the first die, and a third die and a fourth die disposed on the second die. The first die has a first metallization structure, and the first metallization structure includes first through die vias. The second die has a second metallization structure, and second metallization structure includes second through die vias. The first through die vias are bonded with the second through die vias, and sizes of the first through die vias are different from sizes of the second through die vias. The third and fourth dies are disposed side-by-side and are bonded with the second through die vias.

A first semiconductor structure having a first metallic structure that has a convex outermost surface and a second semiconductor structure having a second metallic structure that has a concave outermost surface are first provided. The first and second metallic structures are provided utilizing liner systems that have an opposite galvanic reaction to the metal or metal alloy that constitutes the first and second metallic structures such that during a planarization process the metal liners have a different removal rate than the metal or metal alloy that constitutes the first and second metallic structures. The first semiconductor structure and the second semiconductor structure are then bonded together such that the convex outermost surface of the first metallic structure is in direct contact with the concave outermost surface of the second metallic structure.

Hybrid bonded die stacks, related apparatuses, systems, and methods of fabrication are disclosed. One or both of an integrated circuit (IC) die hybrid bonding region and a base substrate hybrid bonding region are surrounded by superhydrophobic structures that have a contact angle not less than 150 degrees. The hybrid bonding regions are brought together with a liquid droplet therebetween, and capillary forces cause the IC die to self-align. The liquid droplet is pinned to the hybrid bonding regions by the superhydrophobic structures. A hybrid bond is formed by evaporating the droplet and a subsequent anneal.

A method of forming a semiconductor package includes the following operations. A first integrated circuit structure is provided, and the first integrated circuit structure includes a first substrate and a silicon layer over the first substrate. A plasma treatment is performed to transform a top portion of the silicon layer to a first bonding layer on the remaining silicon layer of the first integrated circuit structure. A second integrated circuit structure is provided, and the second integrated circuit structure includes a second substrate and a second bonding layer over the second substrate. The second integrated circuit structure is bonded to the first integrated circuit structure through the second bonding layer of the second integrated circuit structure and the first bonding layer of the first integrated circuit structure.

A semiconductor package may include a lower structure, and an upper structure on the lower structure. The lower structure may include a first semiconductor substrate, first pads on the first semiconductor substrate, and a first insulating layer enclosing the first pads. The upper structure includes a second semiconductor substrate, second pads on the second semiconductor substrate, and a second insulating layer enclosing the second pads. A side surface of the lower structure and a side surface of the upper structure form a stepwise structure near a bonding surface between the lower structure and the upper structure. The first insulating layer includes a protruding portion that extends to a level higher than a top surface of the first insulating layer and is inserted in the second insulating layer.

A semiconductor device structure and method for manufacturing the same are provided. The semiconductor device structure includes a first substrate, a second substrate, and a hybrid bond structure. The second substrate is bonded to the first substrate by the hybrid bond structure. The hybrid bond structure includes a dielectric structure and a conductive structure. The dielectric structure defines an air gap therein.

A semiconductor device structure and method for manufacturing the same are provided. The semiconductor device structure includes a first substrate, a second substrate, and a hybrid bond structure. The second substrate is bonded to the first substrate by the hybrid bond structure. The hybrid bond structure includes a dielectric structure and a conductive structure. The dielectric structure defines an air gap therein.