A semiconductor device having a first semiconductor section including a first wiring layer at one side thereof; a second semiconductor section including a second wiring layer at one side thereof, the first and second semiconductor sections being secured together with the respective first and second wiring layer sides of the first and second semiconductor sections facing each other; a conductive material extending through the first semiconductor section to the second wiring layer of the second semiconductor section and by means of which the first and second wiring layers are in electrical communication; and an opening, other than the opening for the conductive material, which extends through the first semiconductor section to the second wiring layer.

A semiconductor device having a first semiconductor section including a first wiring layer at one side thereof; a second semiconductor section including a second wiring layer at one side thereof, the first and second semiconductor sections being secured together with the respective first and second wiring layer sides of the first and second semiconductor sections facing each other; a conductive material extending through the first semiconductor section to the second wiring layer of the second semiconductor section and by means of which the first and second wiring layers are in electrical communication; and an opening, other than the opening for the conductive material, which extends through the first semiconductor section to the second wiring layer.

A SiC semiconductor device is provided that is capable of improving the detection accuracy of the current value of a principal current detected by a current sensing portion by restraining heat from escaping from the current sensing portion to a wiring member joined to a sensing-side surface electrode. The semiconductor device 1 includes a SiC semiconductor substrate, a source portion 27 including a principal-current-side unit cell 34, a current sensing portion 26 including a sensing-side unit cell 40, a source-side surface electrode 5 disposed above the source portion 27, and a sensing-side surface electrode 6 that is disposed above the current sensing portion 26 and that has a sensing-side pad 15 to which a sensing-side wire is joined, and, in the semiconductor device 1, the sensing-side unit cell 40 is disposed so as to avoid being positioned directly under the sensing-side pad 15.

A method of generating a wire loop profile in connection with a semiconductor package is provided. The method includes the steps of: (a) providing package data related to the semiconductor package; and (b) creating a loop profile of a wire loop of the semiconductor package, the loop profile including a tolerance band along at least a portion of a length of the wire loop.

A method includes attaching a first portion of a preformed metal micro-wire to a multilayer structure. The preformed metal micro-wire has a diameter of 10 microns or less. The method also includes attaching a second portion of the preformed metal micro-wire to the multilayer structure.

Provided here are: an electrically-conductive semiconductor substrate with which a semiconductor circuit is formed; an insulating film deposited on a major surface of the electrically-conductive semi-conductor substrate; and a bonding pad having fixing parts fixed onto the insulating film, side wall parts rising up from the fixing parts, and an electrode part connected to the side wall parts and disposed in parallel to the major surface; wherein the electrode part forms, together with the insulating film, a gap region therebetween, and portions of the electrode part where it is connected to the side wall parts are configured to have at least one of: a positional relationship in which they sandwich therebetween a central portion of the electrode part in its bonding region to be bonded to a bonding wire; and a positional relationship in which they surround the central portion.

An integrated circuit has an isolation capacitor structure that reduces the risk of breakdown from high electric fields at the edge of the top metal plate of the capacitor. The capacitor structure includes a bottom metal plate above a substrate. A first dielectric layer of a first dielectric material is formed between the bottom metal plate and the top metal plate. The capacitor structure also includes a thin narrow ring formed of a second dielectric material located under a portion of the top metal plate. The second dielectric material has a higher dielectric constant than the first dielectric material. The thin narrow ring follows the shape of the edge of the top metal plate with a portion of the ring underneath the top metal plate and a portion outside the edge of the top metal plate to thereby be located at a place of the maximum electric field.

A semiconductor device capable of suppressing propagation of a crack caused by a temperature cycle at a bonding part between a bonding pad and a bonding wire is provided. A semiconductor device according to an embodiment includes a semiconductor chip having bonding pads and bonding wires. The bonding pad includes a barrier layer and a bonding layer formed on the barrier layer and formed of a material containing aluminum. The bonding wire is bonded to the bonding pad and formed of a material containing copper. An intermetallic compound layer formed of an intermetallic compound containing copper and aluminum is formed so as to reach the barrier layer from the bonding wire in at least a part of the bonding part between the bonding pad and the bonding wire.

A semiconductor device includes a conductive support member, a first semiconductor element, a second semiconductor element, an insulating element, and a sealing resin. The conductive support member includes a first die pad and a second die pad, which are separated from each other in a first direction. The first die pad and the second die pad overlap each other when viewed along the first direction. When viewed along a thickness direction, a peripheral edge of the first die pad has a first near-angle portion including a first end portion in a second direction orthogonal to both the thickness direction and the first direction. The first near-angle portion is separated from the second die pad in the first direction toward the first end portion in the second direction.

According to one embodiment, a semiconductor device includes a substrate with a first terminal, a first semiconductor memory chip on the substrate and having a first pad, and a second semiconductor memory chip on the first semiconductor memory chip and having a second pad. A first bonding wire connects to the first terminal and both the first pad and the second pad. A second bonding wire connects to the first terminal and one of the first pad or the second pad from a coordinate position offset from a coordinate position of the first bonding wire.