A method of fabricating a contact hole and a fuse hole includes providing a dielectric layer. A conductive pad and a fuse are disposed within the dielectric layer. Then, a first mask is formed to cover the dielectric layer. Later, a first removing process is performed by taking the first mask as a mask to remove part the dielectric layer to form a first trench. The conductive pad is disposed directly under the first trench and does not expose through the first trench. Subsequently, the first mask is removed. After that, a second mask is formed to cover the dielectric layer. Then, a second removing process is performed to remove the dielectric layer directly under the first trench to form a contact hole and to remove the dielectric layer directly above the fuse by taking the second mask as a mask to form a fuse hole.

There is provided a solid state imaging apparatus, including: an optical film layer on which a solid state image sensor is mounted; a multifunctional chip laminated at a periphery of the solid state image sensor in the optical film layer being electrically contacted with the optical film layer via a metal body; a sealing resin layer for sealing the periphery where the multifunctional chip is laminated on the optical film layer; and a concave structure for blocking a flow of the sealing resin in a liquid state when the sealing resin layer is formed at the periphery of the sealing resin layer. Also, a method of producing the solid state imaging apparatus is also provided.

In various embodiments, a chip package is provided. The chip package may include a chip, a metal contact structure including a non-noble metal and electrically contacting the chip, a packaging material, and a protective layer including or essentially consisting of a portion formed at an interface between a portion of the metal contact structure and the packaging material, wherein the protective layer may include a noble metal, wherein the portion of the protective layer may include a plurality of regions free from the noble metal, and wherein the regions free from the noble metal may provide an interface between the packaging material and the non-noble metal of the metal contact structure.

A semiconductor device including a first material layer adjacent to a second material layer, a first via passing through the first material layer and extending into the second material layer, and a second via extending into the first material layer, where along a common cross section parallel to an interface between the two material layers, the first via has a cross section larger than that of the second via.

A semiconductor device includes: a semiconductor substrate with a first conductivity type; a semiconductor layer with a second conductivity type formed on the semiconductor substrate; a drain region with the second conductivity type and a source region with the second conductivity type formed to be spaced apart from each other in a surface region of the semiconductor layer; a drain buffer region with the second conductivity type formed in the semiconductor substrate directly under the drain region and in the semiconductor layer; a conductivity type well region with the second conductivity type formed on the semiconductor layer between the drain region and the drain buffer region; and a drain metal formed on the drain region to be electrically connected to the drain region and to overlap the well region in a plan view.

A packaging structure and a method for fabricating the packaging structure are provided. The packaging structure includes a base substrate including a solder pad body region and a trench region adjacent to and around the solder pad body region. The packaging structure also includes a passivation layer on a surface of the base substrate and exposing the solder pad body region and the trench region. In addition, the packaging structure includes a main body solder pad on the solder pad body region of the base substrate, and one or more trenches on the trench region of the base substrate and between the passivation layer and the main body solder pad. Further, the packaging structure includes a bonding conductive wire having one end connected to the main body solder pad.

A semiconductor device having a first semiconductor section including a first wiring layer at one side thereof; a second semiconductor section including a second wiring layer at one side thereof, the first and second semiconductor sections being secured together with the respective first and second wiring layer sides of the first and second semiconductor sections facing each other; a conductive material extending through the first semiconductor section to the second wiring layer of the second semiconductor section and by means of which the first and second wiring layers are in electrical communication; and an opening, other than the opening for the conductive material, which extends through the first semiconductor section to the second wiring layer.

A semiconductor device having a first semiconductor section including a first wiring layer at one side thereof; a second semiconductor section including a second wiring layer at one side thereof, the first and second semiconductor sections being secured together with the respective first and second wiring layer sides of the first and second semiconductor sections facing each other; a conductive material extending through the first semiconductor section to the second wiring layer of the second semiconductor section and by means of which the first and second wiring layers are in electrical communication; and an opening, other than the opening for the conductive material, which extends through the first semiconductor section to the second wiring layer.

A minute transistor is provided. A transistor with low parasitic capacitance is provided. A transistor having high frequency characteristics is provided. A semiconductor device including the transistor is provided. A semiconductor device includes a first opening, a second opening, and a third opening which are formed by performing first etching and second etching. By the first etching, the first insulator is etched for forming the first opening, the second opening, and the third opening. By the second etching, the first metal oxide, the second insulator, the third insulator, the fourth insulator, the second metal oxide, and the fifth insulator are etched for forming the first opening; the first metal oxide, the second insulator, and the third insulator are etched for forming the second opening; and the first metal oxide is etched for forming the third opening.

A microelectronic device includes a metal layer on a first dielectric layer. An etch stop layer is disposed over the metal layer and on the dielectric layer directly adjacent to the metal layer. The etch stop layer includes a metal oxide, and is less than 10 nanometers thick. A second dielectric layer is disposed over the etch stop layer. The second dielectric layer is removed from an etched region which extends down to the etch stop layer. The etched region extends at least partially over the metal layer. In one version of the microelectronic device, the etch stop layer may extend over the metal layer in the etched region. In another version, the etch stop layer may be removed in the etched region. The microelectronic device is formed by etching the second dielectric layer using a plasma etch process, stopping on the etch stop layer.