An integrated circuit has a substrate which includes a semiconductor material, and an interconnect region disposed on the substrate. The integrated circuit includes a thermal routing trench in the substrate. The thermal routing trench includes a cohered nanoparticle film in which adjacent nanoparticles are cohered to each other. The thermal routing trench has a thermal conductivity higher than the semiconductor material contacting the thermal routing trench. The cohered nanoparticle film is formed by an additive process.

A power semiconductor device includes a semiconductor body configured to conduct a load current. A load terminal electrically connected with the semiconductor body is configured to couple the load current into and/or out of the semiconductor body. The load terminal includes a metallization having a frontside and a backside. The backside interfaces with a surface of the semiconductor body. The frontside is configured to interface with a wire structure having at least one wire configured to conduct at least a part of the load current. The frontside has a lateral structure formed at least by at least one local elevation of the metallization. The local elevation has a height in an extension direction defined by a distance between the base and top of the local elevation and, in a first lateral direction perpendicular to the extension direction, a base width at the base and a top width at the top.

A solid-state imaging apparatus includes: a solid-state imaging device photoelectrically converting light taken by a lens; and a light shielding member shielding part of light incident on the solid-state imaging device from the lens, wherein an angle made between an edge surface of the light shielding member and an optical axis direction of the lens is larger than an incident angle of light to be incident on an edge portion of the light shielding member.

In a method for producing a semi-conductor module (10) comprising at least two semi-conductor chips (12, 14) and an interposer (20) which has electrically conductive structures (28) connecting the semi-conductor chips (12, 14) to one another, the interposer (20) is printed directly onto a first (12) of the semi-conductor chips. When the interposer (20) is printed on, the electrically conductive structures (28) are produced by means of electrically conductive ink (68). The second semi-conductor chip (14) is mounted on the interposer (20) such that the two semi-conductor chips (12, 14) are arranged one above the other and that the interposer (20) forms an intermediate layer between the two semi-conductor chips (12, 14).

A photoelectric conversion device includes a first semiconductor substrate including a photoelectric conversion unit for generating a signal charge in accordance with an incident light, and a second semiconductor substrate including a signal processing unit for processing an electrical signal on the basis of the signal charge generated in the photoelectric conversion unit. The signal processing unit is situated in an orthogonal projection area from the photoelectric conversion unit to the second semiconductor substrate. A multilayer film including a plurality of insulator layers is provided between the first semiconductor substrate and the second semiconductor substrate. The thickness of the second semiconductor substrate is smaller than 500 micrometers. The thickness of the second semiconductor substrate is greater than the distance from the second semiconductor substrate and a light-receiving surface of the first semiconductor substrate.

A bonding wire for a semiconductor device includes a Cu alloy core material and a Pd coating layer formed on a surface thereof. Containing an element that provides bonding reliability in a high-temperature environment improves the bonding reliability of the ball bonded part in high temperature. Furthermore, making an orientation proportion of a crystal orientation <100> angled at 15 degrees or less to a wire longitudinal direction among crystal orientations in the wire longitudinal direction 30% or more when measuring crystal orientations on a cross-section of the core material in a direction perpendicular to a wire axis of the bonding wire, and making an average crystal grain size in the cross-section of the core material in the direction perpendicular to the wire axis of the bonding wire 0.9 to 1.5 m provides a strength ratio of 1.6 or less.

An insulating film is formed such that the insulating film covers a source electrode and a gate electrode, and an opening portion exposing a portion of the source electrode and an opening portion exposing a portion of the gate electrode are formed in the insulating film. A plated layer is formed over the source electrode exposed in the opening portion, and a plated layer is formed over the gate electrode exposed in the opening portion. A source pad is formed of the portion of the source electrode exposed in the opening portion, and the plated layer, and a gate pad is formed of the portion of the gate electrode exposed in the opening portion, and the plated layer. An area of the opening portion for the gate pad is smaller than an area of the opening portion for the source pad, and a thickness of the plated layer over the gate electrode is greater than a thickness of the plated layer over the source electrode.

A fluidic assembly method is provided that uses a counterbore pocket structure. The method is based upon the use of a substrate with a plurality of counterbore pocket structures formed in the top surface, with each counterbore pocket structure having a through-hole to the substrate bottom surface. The method flows an ink with a plurality of objects over the substrate top surface. As noted above, the objects may be micro-objects in the shape of a disk. For example, the substrate may be a transparent substrate and the disks may be light emitting diode (LED) disks. Simultaneously, a suction pressure is created at the substrate bottom surface. In response to the suction pressure from the through-holes, the objects are drawn into the counterbore pocket structures. Also provided is a related fluidic substrate assembly.

A semiconductor structure includes a substrate including a first surface, a second surface opposite to the first surface and a recess recessed from the first surface towards the second surface; a conductive layer disposed over the first surface and within the recess; and a passivation disposed over the first surface and partially covering the conductive layer, wherein the conductive layer disposed within the recess is exposed from the passivation.

A bonding wire for a semiconductor device, characterized in that the bonding wire includes a Cu alloy core material and a Pd coating layer formed on a surface of the Cu alloy core material, the bonding wire contains an element that provides bonding reliability in a high-temperature environment, and a strength ratio defined by the following Equation (1) is 1.1 to 1.6:

Strength ratio=ultimate strength/0.2% offset yield strength.(1)