Patent classifications
H01L2224/48463
SEMICONDUCTOR DEVICE
A semiconductor device is provided that includes a semiconductor substrate; an insulating film that is provided on the semiconductor substrate, has an opening through which the semiconductor substrate is exposed, and contains oxygen; a first barrier metal portion that is provided at least on a bottom portion of the opening and in which one or more kinds of films are laminated; and an upper electrode provided above the insulating film. The barrier metal is not provided between an upper surface of the insulating film and the upper electrode, or the semiconductor device further comprises a second barrier metal portion between the upper surface of the insulating film and the upper electrode, the second barrier metal portion having a configuration different from that of the first barrier metal portion.
Integrated circuit device having pads structure formed thereon and method for forming the same
The invention is to provide a structure of IC pad and its forming method. The structure is arranged in an insulation layer and is comprised of a lower electric-conduction layer, a compound layer structure and a pad layer. The lower electric-conduction layer is arranged at an appropriate position in the insulation layer and is connected to an electric potential. The compound layer structure is arranged on the insulation layer and is composed of at least one electric-conduction layer and at least one electric-conduction connecting layer, both are inter-overlapped to each other. The pad layer is arranged on the compound layer structure.
Integrated circuit device having pads structure formed thereon and method for forming the same
The invention is to provide a structure of IC pad and its forming method. The structure is arranged in an insulation layer and is comprised of a lower electric-conduction layer, a compound layer structure and a pad layer. The lower electric-conduction layer is arranged at an appropriate position in the insulation layer and is connected to an electric potential. The compound layer structure is arranged on the insulation layer and is composed of at least one electric-conduction layer and at least one electric-conduction connecting layer, both are inter-overlapped to each other. The pad layer is arranged on the compound layer structure.
Via for Component Electrode Connection
Embodiments provide a high aspect ratio via for coupling a top electrode of a vertically oriented component to the substrate, where the top electrode of the component is coupled to the via by a conductive bridge, and where the bottom electrode of the component is coupled to substrate. Some embodiments provide for mounting the component by a component wafer and separating the components while mounted to the substrate. Some embodiments provide for mounting individual components to the substrate.
STILTED PAD STRUCTURE
Various embodiments of the present disclosure are directed towards an integrated circuit (IC) chip comprising a stilted pad structure. A wire underlies a semiconductor substrate on a frontside of the semiconductor substrate. Further, a trench isolation structure extends into the frontside of the semiconductor substrate. The stilted pad structure is inset into a backside of the semiconductor substrate that is opposite the frontside. The stilted pad structure comprises a pad body and a pad protrusion. The pad protrusion underlies the pad body and protrudes from the pad body, through a portion of the semiconductor substrate and the trench isolation structure, towards the wire. The pad body overlies the portion of the semiconductor substrate and is separated from the trench isolation structure by the portion of the semiconductor substrate.
Via for component electrode connection
Embodiments provide a high aspect ratio via for coupling a top electrode of a vertically oriented component to the substrate, where the top electrode of the component is coupled to the via by a conductive bridge, and where the bottom electrode of the component is coupled to substrate. Some embodiments provide for mounting the component by a component wafer and separating the components while mounted to the substrate. Some embodiments provide for mounting individual components to the substrate.
METHOD FOR FORMING BALL IN BONDING WIRE
The present invention provides a ball forming method for forming a ball portion at a tip of a bonding wire which includes a core material mainly composed of Cu, and a coating layer mainly composed of Pd and formed over a surface of the core material, wherein the ball portion is formed in non-oxidizing atmosphere gas including hydrocarbon which is gas at room temperature and atmospheric pressure, the method being capable of improving Pd coverage on a ball surface in forming a ball at a tip of the Pd-coated Cu bonding wire.
MICRO-TRANSFORMER WITH MAGNETIC FIELD CONFINEMENT AND MANUFACTURING METHOD OF THE SAME
A dielectric structure extends over the substrate and a transformer is integrated in the dielectric structure. The transformed includes a first winding in the dielectric layer at a first height and a second winding in the dielectric layer at a second height greater than the first height. The first and second windings are magnetically coupleable to one another. A magnetic element is positioned in alignment with the first and second windings. In one implementation, the magnetic element underlies the first winding in a position between the substrate and the first winding. In another implementation, the magnetic element overlies the second winding.
ELECTRONIC DEVICE, ELECTRONIC DEVICE APPARATUS, ELECTRONIC APPARATUS, AND MOVING OBJECT
An electronic device includes a base body, a functional element disposed on the base body, a wiring disposed on the base body and electrically connected to the functional element, and a terminal disposed on the base body and electrically connected to the wiring, wherein the terminal includes a non-overlapping region which does not overlap with the wiring. Further, the terminal includes an overlapping region which overlaps with the wiring.
Electronic device with integrated galvanic isolation, and manufacturing method of the same
An electronic device includes a semiconductor body and a dielectric layer extending over the semiconductor body. A galvanic isolation module includes a first metal region extending in the dielectric layer at a first height and a second metal region extending in the dielectric layer at a second height greater than the first height. The first and second metal regions are capacitively or magnetically coupleable together. The second metal region includes a side wall and a bottom wall coupled to one another through rounded surface portions.