An electrical contact structure (an MIS contact) includes one or more conductors (M-Layer), a semiconductor (S-Layer), and an interfacial dielectric layer (I-Layer) of less than 4 nm thickness disposed between and in contact with both the M-Layer and the S-Layer. The I-Layer is an oxide of a metal or a semiconductor. The conductor of the M-Layer that is adjacent to and in direct contact with the I-Layer is a metal oxide that is electrically conductive, chemically stable and unreactive at its interface with the I-Layer at temperatures up to 450° C. The electrical contact structure has a specific contact resistivity of less than or equal to approximately 10.sup.−5-10.sup.−7 Ω-cm.sup.2 when the doping in the semiconductor adjacent the MIS contact is greater than approximately 2×10.sup.19 cm.sup.−3 and less than approximately 10.sup.−8 Ω-cm.sup.2 when the doping in the semiconductor adjacent the MIS contact is greater than approximately 10.sup.20 cm.sup.−3.

A semiconductor device is provided with: a substrate; a first region provided above the substrate; a second region provided away from the first region in a first direction; a third region provided between the first region and the second region, the third region facing an electrode portion; a fourth region provided between the first region and the third region; and a fifth region provided between the second region and the third region. The fourth and fifth regions include carbon (C). Carbon concentrations in the first and second regions are lower than carbon concentrations in the fourth and fifth regions.

A lateral DMOS transistor structure includes a substrate of a first dopant polarity, a body region of the first dopant polarity, a source region, a drift region of a second dopant polarity, a drain region, a channel region, a gate structure over the channel region, a hybrid contact implant, of the second dopant polarity, in the source region, and a respective metal contact on or within each of the source region, gate structure, and drain region. The hybrid contact implant and the metal contact together form a hybrid contact defining first, second, and third electrical junctions. The first junction is a Schottky junction formed vertically between the source metal contact and the body. The second junction is an ohmic junction formed laterally between the source metal contact and the hybrid contact implant. The third junction is a rectifying PN junction between the hybrid contact implant and the channel region.

One illustrative transistor device disclosed herein includes a gate structure positioned above a semiconductor substrate and a source region and a drain region, each of which comprise an epi cavity with a bottom surface and a side surface. The transistor further includes an interface layer positioned on at least one of the side surface and the bottom surface of the epi cavity in each of the source/drain regions, wherein the interface layer comprises a non-semiconductor material and an epi semiconductor material positioned on at least an upper surface of the interface layer in the epi cavity in each of the source region and the drain region.

A lateral DMOS transistor structure includes a substrate of a first dopant polarity, a body region of the first dopant polarity, a source region, a drift region of a second dopant polarity, a drain region, a channel region, a gate structure over the channel region, a hybrid contact implant, of the second dopant polarity, in the source region, and a respective metal contact on or within each of the source region, gate structure, and drain region. The hybrid contact implant and the metal contact together form a hybrid contact defining first, second, and third electrical junctions. The first junction is a Schottky junction formed vertically between the source metal contact and the body. The second junction is an ohmic junction formed laterally between the source metal contact and the hybrid contact implant. The third junction is a rectifying PN junction between the hybrid contact implant and the channel region.

A semiconductor device may include a semiconductor layer, spaced apart source and drain regions in the semiconductor layer with a channel region extending therebetween, and a gate on the channel region. The semiconductor device may further include a body contact in the semiconductor layer and comprising a body contact dopant diffusion blocking superlattice extending through the body contact to divide the body contact into a first body contact region and an second body contact region with the second body contact region having a same conductivity and higher dopant concentration than the first body contact region. The body contact dopant diffusion blocking superlattice may include a respective plurality of stacked groups of layers, with each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions.

A method of forming a semiconductor device can be provided by forming an opening that exposes a surface of an elevated source/drain region. The size of the opening can be reduced and a pre-amorphization implant (PAI) can be performed into the elevated source/drain region, through the opening, to form an amorphized portion of the elevated source/drain region. A metal-silicide can be formed from a metal and the amorphized portion.

A method for making a semiconductor device may include forming spaced apart source and drain regions in a semiconductor layer with a channel region extending therebetween. At least one of the source and drain regions may be divided into a lower region and an upper region by a dopant diffusion blocking superlattice with the upper region having a same conductivity and higher dopant concentration than the lower region. The dopant diffusion blocking superlattice may include a plurality of stacked groups of layers, with each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The method may further include forming a gate on the channel region.

An electrical device in which an interface layer is disposed in between and in contact with a conductor and a semiconductor.

An electrical device in which an interface layer is disposed in between and in contact with a conductor and a semiconductor.