An interlayer is used to reduce Fermi-level pinning phenomena in a semiconductive device with a semiconductive substrate. The interlayer may be a rare-earth oxide. The interlayer may be an ionic semiconductor. A metallic barrier film may be disposed between the interlayer and a metallic coupling. The interlayer may be a thermal-process combination of the metallic barrier film and the semiconductive substrate. A process of forming the interlayer may include grading the interlayer. A computing system includes the interlayer.

An electrical device in which an interface layer is disposed in between and in contact with a conductor and a semiconductor.

To stably form a low-resistance electrical coupling between a metal and a semiconductor.

An electrical coupling structure includes: a semiconductor layer; a metal layer; and an intermediate layer that is held between the semiconductor layer and the metal layer, and includes an insulating layer provided on the semiconductor layer side and a two-dimensional material layer provided on the metal layer side.

A manufacturing method for a LDMOS semiconductor device may include steps of forming a P-type layer on a P-type substrate; forming a P-type body region and an N-type well under the P-type layer; forming a field oxide on the P-type layer; forming a gate oxide on the P-type body region and field oxide; forming a gate polysilicon on top of the gate oxide; depositing a gate metal silicide on top of the gate polysilicon; depositing a thin film on top of the field oxide, P-type body region and gate silicide; forming a dielectric layer on top of the thin film; forming a first trench in the dielectric layer; forming a second trench underneath the first trench; depositing a metal layer on top of the dielectric layer and filling into the first and second trenches; and removing the metal on top of the dielectric layer.

A method for making a semiconductor device may include forming spaced apart source and drain regions in a semiconductor layer with a channel region extending therebetween. At least one of the source and drain regions may be divided into a lower region and an upper region by a dopant diffusion blocking superlattice with the upper region having a same conductivity and higher dopant concentration than the lower region. The dopant diffusion blocking superlattice may include a plurality of stacked groups of layers, with each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The method may further include forming a gate on the channel region.

A semiconductor device may include a semiconductor layer, spaced apart source and drain regions in the semiconductor layer with a channel region extending therebetween, and a gate on the channel region. The semiconductor device may further include a body contact in the semiconductor layer and comprising a body contact dopant diffusion blocking superlattice extending through the body contact to divide the body contact into a first body contact region and an second body contact region with the second body contact region having a same conductivity and higher dopant concentration than the first body contact region. The body contact dopant diffusion blocking superlattice may include a respective plurality of stacked groups of layers, with each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions.

An electrical contact structure (an MIS contact) includes one or more conductors (M-Layer), a semiconductor (S-Layer), and an interfacial dielectric layer (I-Layer) of less than 4 nm thickness disposed between and in contact with both the M-Layer and the S-Layer. The I-Layer is an oxide of a metal or a semiconductor. The conductor of the M-Layer that is adjacent to and in direct contact with the I-Layer is a metal oxide that is electrically conductive, chemically stable and unreactive at its interface with the I-Layer at temperatures up to 450 C. The electrical contact structure has a specific contact resistivity of less than or equal to approximately 10.sup.5-10.sup.7 -cm.sup.2 when the doping in the semiconductor adjacent the MIS contact is greater than approximately 210.sup.19 cm.sup.3 and less than approximately 10.sup.8 -cm.sup.2 when the doping in the semiconductor adjacent the MIS contact is greater than approximately 10.sup.20 cm.sup.3.

A semiconductor device is provided with: a substrate; a first region provided above the substrate; a second region provided away from the first region in a first direction; a third region provided between the first region and the second region, the third region facing an electrode portion; a fourth region provided between the first region and the third region; and a fifth region provided between the second region and the third region. The fourth and fifth regions include carbon (C). Carbon concentrations in the first and second regions are lower than carbon concentrations in the fourth and fifth regions.

An electrical contact structure (an MIS contact) includes one or more conductors (M-Layer), a semiconductor (S-Layer), and an interfacial dielectric layer (I-Layer) of less than 4 nm thickness disposed between and in contact with both the M-Layer and the S-Layer. The I-Layer is an oxide of a metal or a semiconductor. The conductor of the M-Layer that is adjacent to and in direct contact with the I-Layer is a metal oxide that is electrically conductive, chemically stable and unreactive at its interface with the I-Layer at temperatures up to 450 C. The electrical contact structure has a specific contact resistivity of less than or equal to approximately 10.sup.5-10.sup.7 -cm.sup.2 when the doping in the semiconductor adjacent the MIS contact is greater than approximately 210.sup.19 cm.sup.3 and less than approximately 10.sup.8 -cm.sup.2 when the doping in the semiconductor adjacent the MIS contact is greater than approximately 10.sup.20 cm.sup.3.

A semiconductor component is disclosed. The semiconductor component can include: a semiconductor layer injected with a same type of dopant; a gate electrode formed above the semiconductor layer with a gate insulation film positioned in-between; a dielectric layer formed on the semiconductor layer at both sides of the gate electrode; and source/drain electrodes each formed on the dielectric layer.