A molding is formed by laminating an aggregate of SiC and a paste containing Si and C powders on an epitaxial layer of SiC formed on a support substrate of SiC to form an intermediate sintered body in which polycrystalline SiC is produced from the Si and C powders by reaction sintering, free Si is carbonized to SiC to form a sintered body layer, and the support substrate is removed from the epitaxial layer to form a semiconductor substrate in which the epitaxial layer and the sintered body layer are laminated.

An MTP (Many Times Programmable) memory cell for integrated circuit memory arrays is described. The cell includes an MTP device and a thyristor interconnected so that the MTP device triggers the thyristor to turn on during a Read or Verify operation. The difference in threshold voltages between a data memory cell and a reference memory cell is used to determine the information in the data memory cell. Different memory cell structures may be constructed for different memory array requirements.

A two-transistor memory cell based upon a thyristor for an SRAM integrated circuit is described together with a process for fabricating it. The memory cell can be implemented in different combinations of MOS and bipolar select transistors, or without select transistors, with thyristors in a semiconductor substrate with shallow trench isolation. Standard CMOS process technology can be used to manufacture the SRAM.

A two-transistor memory cell based upon a thyristor for an SRAM integrated circuit is described together with a process for fabricating it. The memory cell can be implemented in different combinations of MOS and bipolar select transistors, or without select transistors, with thyristors in a semiconductor substrate with shallow trench isolation. Standard CMOS process technology can be used to manufacture the SRAM.

A method for controlling a first switch and a second switch is suggested, wherein each switch is an RC-IGBT and wherein both switches are arranged as a half-bridge circuit. The method includes: controlling the first switch in an IGBT-mode; controlling the second switch such that it becomes desaturated when being in a DIODE-mode; wherein controlling the second switch starts before and lasts at least as long as the first switch changes its IGBT-mode from blocking state to conducting state.

A two-transistor memory cell based upon a thyristor for an SRAM integrated circuit is described together with a process for fabricating it. The memory cell can be implemented in different combinations of MOS and bipolar select transistors, or without select transistors, with thyristors in a semiconductor substrate with shallow trench isolation. Standard CMOS process technology can be used to manufacture the SRAM.

An MTP (Many Times Programmable) memory cell for integrated circuit memory arrays is described. The cell includes an MTP device and a thyristor interconnected so that the MTP device triggers the thyristor to turn on during a Read or Verify operation. The difference in threshold voltages between a data memory cell and a reference memory cell is used to determine the information in the data memory cell. Different memory cell structures may be constructed for different memory array requirements.

A module (100) is specified, the module (100) comprising a first module connection (108), a second module connection (109), an energy store (105), a first electrical switch (101) and a second electrical switch (102), wherein a switchable bypass device (1) is arranged between the first module connection (108) and the second module connection (109) and wherein the switchable bypass device (1) is configured to remain in a bidirectional current conducting state in response to a single trigger pulse.

A semiconductor device according to an embodiment includes a substrate, first and second pillar electrodes extending along a vertical direction substantially perpendicular to a surface of the substrate, and a plurality of memory cells disposed between the first and second pillar electrodes. Each of the plurality of memory cells includes first and second shared device layers that are disposed adjacent to the first and second pillar electrodes, respectively, and extend along the vertical direction, first and second base device layers disposed between the first and second shared device layers, and a control gate electrode disposed on one of the first and second base device layers. Both first and second base device layers are disposed on a plane over the substrate and substantially parallel to the surface of the substrate.