A method for producing a planar semiconductor surface includes forming a workpiece that has a carrier substrate, one or more insulating layers, a semiconductor layer, a first etch stop layer, and a second etch stop layer; forming a contact on the workpiece; biasing the workpiece to a second voltage through the contact; etching the second etch stop layer and part of the first etch stop layer with a photo-electrochemical etching and the second voltage that selectively removes the second etch stop layer faster than the first etch stop layer; biasing the workpiece to a first voltage through the contact; and etching the first etch stop layer and part of the semiconductor layer with the photo-electrochemical etching and the first voltage that selectively removes the first etch stop layer faster than the semiconductor layer to produce a semiconductor device with a planar surface on the semiconductor layer.

A process for manufacturing a silicon carbide device from a body of silicon carbide having a back surface, wherein a first layer of a first metal is formed on the back surface of the body; a second layer of a second metal, different from the first metal, is formed on the first layer to form a multilayer, the first or the second metal being nickel or a nickel alloy and forming a nickel-based layer, another of the first or the second metal being a metal X, capable to form stable compounds with carbon and forming an X-based layer; and the multilayer is annealed to form a mixed layer including nickel silicide and at least one of X carbide or a metal X-carbon ternary compound.

A part is adapted to be used in a semiconductor processing equipment. The part includes a substrate and a protective coating. The protective coating covers at least a part of the substrate, is made of silicon carbide, and has an atomic ratio of carbon in the protective coating increases in a direction away from the substrate while an atomic ratio of silicon in the protective coating decreases in the direction. The atomic ratio of silicon in the protective coating is larger than that of the carbon near the substrate, and the atomic ratio of silicon in the protective coating is smaller than that of carbon near the outer surface of the protective coating. A method for making the part is also provided.

Exemplary methods of semiconductor processing may include providing a silicon-containing precursor to a processing region of a semiconductor processing chamber. A substrate may be disposed within the processing region of the semiconductor processing chamber. The substrate may define one or more features along the substrate. The methods may include depositing a silicon-containing material on the substrate. The silicon-containing material may extend within the one or more features along the substrate. The methods may include providing an oxygen-containing precursor. The methods may include annealing the silicon-containing material with the oxygen-containing precursor. The annealing may cause the silicon-containing material to expand within the one or more features. The methods may include repeating one or more of the operations to iteratively fill the one or more features on the substrate.

Selective gas etching for self-aligned pattern transfer uses a first block and a separate second block formed in a sacrificial layer to transfer critical dimensions to a desired final layer using a selective gas etching process. The first block is a first hardmask material that can be plasma etched using a first gas, and the second block is a second hardmask material that can be plasma etched using a second gas separate from the first gas. The first hardmask material is not plasma etched using the second gas, and the second hardmask material is not plasma etched using the first gas.

A wafer support device according to an embodiment provides a wafer support device. The wafer support device has a support table and a wafer guide portion. The wafer guide portion includes a first chamfered portion and a second chamfered portion. The support table has a support surface that supports the wafer. The wafer guide portion has an annular shape that surrounds the circumference of the wafer supported on the support surface with the central axis extending in a normal direction of the support surface as a center. The first chamfered portion connects an inner circumferential surface and an upper surface of the wafer guide portion, and extends upward from the inner circumferential surface toward the outer circumferential side. The second chamfered portion connects an outer circumferential surface and the upper surface of the wafer guide portion, and extends upward from the outer circumferential surface toward the inner circumferential side.

A method of identifying defects in crystals includes the following steps. A silicon carbide crystal to be identified for defects is sliced to obtain a test piece. An etching process is performed on the test piece. Etching conditions of the etching process includes the following. An etchant including potassium hydroxide is used, and etching is performed at a temperature of 400 C. to 550 C. in an environment where dry air or oxygen is introduced, so as to form etching pits of threading edge dislocations (TED) and threading screw dislocations (TSD) in the test piece. After the etching process is performed, a diameter ratio (TED/TSD) of the etching pits of the threading edge dislocations (TED) and the threading screw dislocations (TSD) observed by an optical microscope in the test piece is in a range of 0.2 to 0.5.