MITIGATING THERMAL IMPACTS ON ADJACENT STACKED SEMICONDUCTOR DEVICES

Abstract

A semiconductor device assembly and associated methods are disclosed herein. The semiconductor device assembly includes (1) a substrate having a first side and a second side opposite the first side; (2) a first set of stacked semiconductor devices at the first side of the substrate; (3) a second set of stacked semiconductor devices adjacent to one side of the first set of stacked semiconductor devices; (4) a third set of stacked semiconductor devices adjacent to an opposite side of the first set of stacked semiconductor devices; and (5) a temperature adjusting component at the second side and aligned with the second set of stacked semiconductor devices. The temperature adjusting component is positioned to absorb the thermal energy and thereby thermally isolate the second set of stacked semiconductor devices from the first set of stacked semiconductor devices.

Claims

1. A semiconductor assembly, comprising: a substrate comprising a first side coupled with a first semiconductor package and a second semiconductor package, the first semiconductor package separated from the second semiconductor package in a first direction; and a temperature adjusting component coupled with a second side of the substrate and configured to draw thermal energy out of the substrate and away from the second semiconductor package, wherein the temperature adjusting component is offset from the first semiconductor package in the first direction, and wherein the temperature adjusting component has a length, in the first direction, that is at least as long as a length of the second semiconductor package, and a width, in a second direction perpendicular to the first direction, that is at least as wide as a width of the second semiconductor package.

2. The semiconductor assembly of claim 1, wherein the length of the temperature adjusting component is greater than the length of the second semiconductor package, and wherein the width of the temperature adjusting component is greater than the width of the second semiconductor package.

3. The semiconductor assembly of claim 2, wherein the second semiconductor package has a first horizontal edge and a second horizontal edge parallel to the first horizontal edge, and wherein the temperature adjusting component extends past the first horizontal edge and past the second horizontal edge in the second direction.

4. The semiconductor assembly of claim 2, wherein the second semiconductor package has a first vertical edge and a second vertical edge parallel to the first vertical edge, and wherein the temperature adjusting component extends past the first vertical edge and past the second vertical edge in the first direction.

5. The semiconductor assembly of claim 1, wherein the length of the temperature adjusting component is greater than the length of the second semiconductor package, and wherein the width of the temperature adjusting component is equal to the width of the second semiconductor package.

6. The semiconductor assembly of claim 5, wherein the second semiconductor package has a first horizontal edge and a second horizontal edge parallel to the first horizontal edge, and wherein the temperature adjusting component aligns with the first horizontal edge and with the second horizontal edge in the second direction.

7. The semiconductor assembly of claim 5, wherein the second semiconductor package has a first vertical edge and a second vertical edge parallel to the first vertical edge, and wherein the temperature adjusting component extends past the first vertical edge and past the second vertical edge in the first direction.

8. The semiconductor assembly of claim 1, wherein the length of the temperature adjusting component is equal to the length of the second semiconductor package, and wherein the width of the temperature adjusting component is equal to the width of the second semiconductor package.

9. The semiconductor assembly of claim 8, wherein the second semiconductor package has a first horizontal edge and a second horizontal edge parallel to the first horizontal edge, and wherein the temperature adjusting component aligns with the first horizontal edge and with the second horizontal edge in the second direction.

10. The semiconductor assembly of claim 8, wherein the second semiconductor package has a first vertical edge and a second vertical edge parallel to the first vertical edge, and wherein the temperature adjusting component aligns with the first vertical edge and with the second vertical edge in the first direction.

11. A semiconductor assembly, comprising: a substrate comprising a first side coupled with a first semiconductor package and a second semiconductor package, the first semiconductor package separated from the second semiconductor package in a first direction; and a temperature adjusting component coupled with a second side of the substrate and configured to draw thermal energy out of the substrate and away from the second semiconductor package, wherein the temperature adjusting component is offset from the first semiconductor package in the first direction, wherein the temperature adjusting component has a width, in a second direction perpendicular to the first direction, that is at least as wide as a width of the second semiconductor package, and wherein the temperature adjusting component extends in the second direction from at least a first horizontal edge of the second semiconductor package to at least a second horizontal edge of the second semiconductor package.

12. The semiconductor assembly of claim 11, wherein the temperature adjusting component has a length, in the first direction, that is less than a length of the second semiconductor package.

13. The semiconductor assembly of claim 12, wherein the temperature adjusting component has a first vertical edge aligned with a first vertical edge of the second semiconductor package, and wherein the temperature adjusting component has a second vertical edge between the first vertical edge of the second semiconductor package and a second vertical edge of the second semiconductor package.

14. The semiconductor assembly of claim 13, wherein the first vertical edge of the temperature adjusting component is between, in the first direction, the first semiconductor package and the second vertical edge.

15. The semiconductor assembly of claim 11, wherein the temperature adjusting component has a length, in the first direction, that is at least as long as a length of the second semiconductor package.

16. A semiconductor assembly, comprising: a substrate comprising a first side coupled with a first semiconductor package and a second semiconductor package, the first semiconductor package separated from the second semiconductor package in a first direction; and a temperature adjusting component coupled with a second side of the substrate and configured to draw thermal energy out of the substrate and away from the second semiconductor package, wherein the temperature adjusting component is offset from the first semiconductor package in the first direction, wherein the temperature adjusting component has a length, in the first direction, that is at least as long as a length of the second semiconductor package, and wherein the temperature adjusting component extends in the first direction from at least a first vertical edge of the second semiconductor package to at least a second vertical edge of the second semiconductor package.

17. The semiconductor assembly of claim 16, wherein the temperature adjusting component has a width, in a second direction perpendicular to the first direction, greater than a width of the second semiconductor package, wherein the second semiconductor package has a first horizontal edge and a second horizontal edge parallel to the first horizontal edge, and wherein the temperature adjusting component extends past the first horizontal edge and past the second horizontal edge in the second direction.

18. The semiconductor assembly of claim 17, wherein the temperature adjusting component extends in the first direction past the first vertical edge of the second semiconductor package, and wherein the temperature adjusting component extends in the first direction past the second vertical edge of the second semiconductor package.

19. The semiconductor assembly of claim 16, wherein the temperature adjusting component has a width, in a second direction perpendicular to the first direction, equal to a width of the second semiconductor package, wherein the second semiconductor package has a first horizontal edge and a second horizontal edge parallel to the first horizontal edge, wherein a first horizontal edge of the temperature adjusting component aligns with the first horizontal edge of the second semiconductor package, and wherein a second horizontal edge of the temperature adjusting component aligns with the second horizontal edge of the second semiconductor package.

20. The semiconductor assembly of claim 19, wherein the temperature adjusting component extends in the first direction past the first vertical edge of the second semiconductor package, and wherein the temperature adjusting component extends in the first direction past the second vertical edge of the second semiconductor package.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0004] Many aspects of the present technology can be better understood with reference to the following drawings. The components in the drawings are not necessarily to scale. Instead, emphasis is placed on illustrating the principles of the present technology.

[0005] FIG. 1A is a schematic cross-sectional view of a semiconductor device assembly in accordance with an embodiment of the present technology.

[0006] FIG. 1B is a schematic bottom view of a semiconductor device assembly in accordance with an embodiment of the present technology.

[0007] FIGS. 2A-2C are schematic bottom views of semiconductor device package assemblies in accordance with embodiments of the present technology.

[0008] FIG. 3 is a schematic, isometric view of a temperature adjusting component in accordance with an embodiment of the present technology.

[0009] FIGS. 4A and 4B are schematic cross-sectional views of semiconductor device package assemblies in accordance with an embodiment of the present technology.

[0010] FIG. 5 is a block diagram illustrating a system that incorporates a semiconductor assembly in accordance with an embodiment of the present technology.

[0011] FIG. 6 is a flowchart illustrating a method in accordance with an embodiment of the present technology.

DETAILED DESCRIPTION

[0012] Specific details of several embodiments of stacked semiconductor die packages and methods of manufacturing such die packages are described below. The term semiconductor device generally refers to a solid-state device that includes one or more semiconductor materials. A semiconductor device can include, for example, a semiconductor substrate, wafer, or die that is singulated from a wafer or substrate. Throughout the disclosure, semiconductor dies are generally described in the context of semiconductor devices but are not limited thereto.

[0013] The term semiconductor device package can refer to an arrangement with one or more semiconductor devices incorporated into a common package. A semiconductor device package can include a housing or casing that partially or completely encapsulates at least one semiconductor device. A semiconductor device package can also include an interposer substrate that carries one or more semiconductor devices and is attached to or otherwise incorporated into the casing. The term semiconductor device assembly can refer to an assembly that includes multiple stacked semiconductor devices. As used herein, the terms vertical, lateral, upper, and lower can refer to relative directions or positions of features in the semiconductor device or package in view of the orientation shown in the Figures. These terms, however, should be construed broadly to include semiconductor devices having other orientations, such as inverted or inclined orientations.

[0014] When using thermal energy to cure two adjacent semiconductor device packages that are close to each other, the thermal energy applied to a first package can adversely affect a second package. For example, excess thermal energy can further harden or otherwise impact a film of the second film such that it cannot properly deform to and/or adhere to connecting semiconductor dies. The present technology provides a solution to address this issue.

[0015] FIG. 1A is a schematic cross-sectional view of a semiconductor device assembly 100 in accordance with an embodiment of the present technology. The semiconductor device assembly 100 includes a base substrate 101, a first set of stacked semiconductor devices 103, and a second set of stacked semiconductor devices 105. The first and second sets of semiconductor devices 103, 105 are adjacent to each other and carried by the base substrate 101. The semiconductor device assembly 100 can also include more than two semiconductor device packages. The first and second sets of stacked semiconductor devices 103, 105 are to be encapsulated or covered by suitable materials such as dielectric materials, epoxy resin, etc. The encapsulated first and second sets of stacked semiconductor devices 103, 105 can be named first and second semiconductor device packages, respectively.

[0016] The first set of stacked semiconductor devices 103 includes multiple semiconductor devices 1031 and multiple curable layers 1033 between or on the semiconductor devices 1031, respectively. In the embodiment illustrated in FIG. 1A, the first set of stacked semiconductor devices 103 includes eight semiconductor devices 1031 and eight curable layers 1033. However, it will be appreciated that the first set of stacked semiconductor devices 103 can have a different number of semiconductor devices 1031 and curable layers 1033.

[0017] The second set of stacked semiconductor devices 105 can also include multiple semiconductor devices 1051 and multiple curable layers 1053 between or on the semiconductor devices 1031, respectively. The embodiment of the second set of stacked semiconductor devices 105 shown in FIG. 1A has eight semiconductor devices 1051 and eight curable layers 1053, but the second set of stacked semiconductor devices 105 can include a different number of semiconductor devices 1051 and curable layers 1053 in other embodiments.

[0018] The curable layers 1033, 1053 can include a die-attaching material for bonding the semiconductor devices 1031, 1051 to one another or to the base substrate 101. The curable layers 1033, 1053 can be a non-conductive film (NCF), a non-conductive paste (NCP), etc. The curable layers 1033, 1053 can also include heat-sensitive or temperature-sensitive materials such that the stiffness or flexibility of the curable layers 1033, 1053 can be manipulated by adjusting the temperature or thermal energy.

[0019] The curable layers 1033 can be cured by applying thermal energy from a thermal component 109 of a bond head 107. In some embodiments, the thermal component 109 can be an external component that is attached to the bond head 107. As shown in FIG. 1A, the heat generated by the thermal component 109 flows through the first semiconductor die package 103 toward the base substrate 101 in direction D.sub.1 and thereby cures the curable layers 1033. A portion of the thermal energy can also flow toward the second set of stacked semiconductor devices 105, as indicated by direction D.sub.2, and then upward to one or more of the curable layers 1053, as indicated by direction D.sub.3. This can adversely affect or more of the curable layers 1053.

[0020] The semiconductor device assembly 100 of the present technology can be manufactured by using a temperature adjusting component 111 configured to inhibit or prevent thermal energy generated by the thermal component 109 from reaching the curable layers 1053 of the second set of stacked semiconductor devices 105. The temperature adjusting component 111 is accordingly configured to at least partially thermally isolate the second set of stacked semiconductor devices 105 from the first set of stacked semiconductor devices 103. As shown in FIG. 1A, the temperature adjusting component 111 can be adjacent to the base substrate 101 and opposite to the second set of stacked semiconductor devices 105. The temperature adjusting component 111 can be in an area A.sub.1 defined by a side 103a of the first set of stacked semiconductor devices 103 and a second side 105b of the second set of stacked semiconductor devices 105. For example, as shown in FIG. 1A, the temperature adjusting component 111 is positioned such that an edge 111a of the temperature adjusting component 111 is aligned with a first side 105a of the second set of stacked semiconductor devices 105. In some embodiments, the temperature adjusting component 111 can be shaped or formed to cover a substantial portion of area A.sub.1. For example, the substantial portion can mean more than 90%, 75%, or 50% in various embodiments.

[0021] The temperature adjusting component 111 can also or alternatively be in an area A.sub.2 and/or an Area A.sub.3. When the temperature adjusting component 111 is in Area A.sub.2, the temperature adjusting component 111 absorbs heat transferred through the base substrate 101 from both sides of the second set of stacked semiconductor devices 105. When the temperature adjusting component 111 is in Area A.sub.3, the temperature adjusting component 111 directly absorbs excessive heat from directly underneath the first set of stacked semiconductor devices 103.

[0022] The temperature adjusting component 111 can be a cooling unit or a heat sink configured to absorb the thermal energy from the thermal component 109 to maintain the temperature of the base substrate 101 within a desired range. The temperature adjusting component 111, for example, can be a passive cooling unit that only absorbs heat energy transferred thereto and cools through conduction and convection to the environment. The temperature adjusting component 111 can alternatively be an active cooling unit that actively cools other components (e.g., the second set of stacked semiconductor devices 105). In such embodiments, the temperature adjusting component 111 can be a thermoelectric component, such as a thermoelectric cooler, a Peltier device, a solid-state refrigerator, etc.

[0023] FIG. 1B a schematic bottom view of the semiconductor device assembly 100 shown in FIG. 1A. The second set of stacked semiconductor devices 105 has a first lateral dimension X.sub.1 and a second lateral dimension Y.sub.1. The first set of stacked semiconductor devices 103 has generally the same lateral dimensions as the second set of stacked semiconductor devices 105. The temperature adjusting component 111 has a first lateral dimension X.sub.2 and a second lateral dimension Y.sub.2. In the embodiment illustrated in FIG. 1B, the first lateral dimension X.sub.2 of the temperature adjusting component 111 is smaller than the first lateral dimension X.sub.1 of the second set of stacked semiconductor devices 105, whereas the second lateral dimension Y.sub.2 of the temperature adjusting component 111 is greater than the second lateral dimension Y.sub.1 of the second set of stacked semiconductor devices 105. The temperature adjusting component 111 can have a rectilinear shape, such as a square, a rectangle (shown in FIG. 1B), etc.

[0024] FIGS. 2A-2C are schematic bottom views of the semiconductor device package assemblies 100 in accordance with embodiments of the present technology. In the embodiment illustrated in FIG. 2A, the first lateral dimension X.sub.2 of the temperature adjusting component 111 is greater than the first lateral dimension X.sub.1 of the second set of stacked semiconductor devices 105, and the second lateral dimension Y.sub.2 of the temperature adjusting component 111 is also greater than the second lateral dimension Y.sub.1 of the second set of stacked semiconductor devices 105. In the embodiment illustrated in FIG. 2B, the first lateral dimension X.sub.2 of the temperature adjusting component 111 is greater than the first lateral dimension X.sub.1 of the second set of stacked semiconductor devices 105, whereas the second lateral dimension Y.sub.2 of the temperature adjusting component 111 is generally the same as the second lateral dimension Y.sub.1 of the second set of stacked semiconductor devices 105. In the embodiment illustrated in FIG. 2C, the first lateral dimension X.sub.2 of the temperature adjusting component 111 is generally the same as the first lateral dimension X.sub.1 of the second set of stacked semiconductor devices 105, and the second lateral dimension Y.sub.2 of the temperature adjusting component 111 is also generally the same as the second lateral dimension Y.sub.1 of the second set of stacked semiconductor devices 105.

[0025] FIG. 3 is a schematic, isometric view of a temperature adjusting component 311 in accordance with an embodiment of the present technology. The temperature adjusting component 311 is a rectangular ring. As shown, the temperature adjusting component 311 has a first external dimension X.sub.3 and a second external dimension Y.sub.3. The temperature adjusting component 311 also has a first inner dimension X.sub.4 and a second inner dimension Y.sub.4. The first external dimension X.sub.3 is greater than the first inner dimension X.sub.4. The second external dimension Y.sub.3 is greater than the second inner dimension Y.sub.4. The difference between the first external dimension X.sub.3 and the first inner dimension X.sub.4 (or the difference between the second external dimension Y.sub.3 and the second inner dimension Y.sub.4) can vary in various embodiments depending on factors such as the dimension of the second set of stacked semiconductor devices 105, a target temperature for curing the curable layers 1033 of the first set of stacked semiconductor devices 103, types of materials of the curable layers 1033, 1053, a distance or gap between the first and second sets of semiconductor devices 103, 105, etc.

[0026] FIG. 4A is a schematic cross-sectional view of a semiconductor device assembly 400 in accordance with an embodiment of the present technology. The semiconductor device assembly 400 includes a base substrate 401, a first set of stacked semiconductor devices 403, a second set of stacked semiconductor devices 405, and a third set of stacked semiconductor devices 406. The second and third sets of stacked semiconductor devices 405 and 406 are on opposite sides of the first set of stacked semiconductor devices 403. The semiconductor device packages 403, 405, and 406 are attached to a front side 401a of the base substrate 401, and the base substrate 401 has a back side 401b. In some embodiments, the semiconductor device assembly 400 can include more than three semiconductor device packages.

[0027] As shown in FIG. 4A, a thermal component 409 of a bond head 407 is used heat the first set of stacked semiconductor devices 403 to bond the semiconductor devices 4031 in the first set of stacked semiconductor devices 403 together. The semiconductor devices 4031 can be bonded by curing films 4033 attached to the semiconductor devices 4031, respectively. The heat generated by the thermal component 409 flows toward the base substrate 401, as indicated by direction D.sub.4.

[0028] The semiconductor device assembly 400 also has a cooling unit 411 attached to the back side 401b of the base substrate 401. The backside cooling unit 411 is configured to inhibit or prevent heat generated by the thermal component 409 from transferring to either the second set of stacked semiconductor devices 405 or the third set of stacked semiconductor devices 406 via the base substrate 401. In some embodiments, the backside cooling unit 411 can be formed with a recess 413, which can effectively prevent the backside cooling unit 411 from absorbing too much heat from the base substrate 401. This may be useful because absorbing too much heat may affect the curing process of curing the films 4033. By this arrangement, the curing process for the films 4033 (e.g., particularly the lowest one in FIG. 4) of the first set of stacked semiconductor devices 403 is not affected by the backside cooling unit 411.

[0029] In some embodiments, the backside cooling unit 411 can be shaped or formed according to the shape, materials, and/or characteristics of the base substrate 401. The dimensions of the recess 413, for example, can be determined based on the thermal conductivity of the base substrate 401 and the load provided by the thermal component 409. For example, in embodiments where the base substrate 401 has a relatively high thermal conductivity, the dimension of the recess 413 can be relatively small. Conversely, when the base substrate 401 has a relatively low thermal conductivity, the dimension of the recess 413 can be relatively large. As shown in FIG. 4A, the recess 413 can have a lateral dimension from a side surface 4055 of the second set of stacked semiconductor devices 405 to a side surface 4065 of the third set of stacked semiconductor devices 406. In some embodiments, the recess 413 can have a lateral dimension the same as the lateral dimension of the first set of stacked semiconductor devices 403 (e.g., from a first side surface 4035 to a second side surface 4037 opposite the first side surface 4035). In some embodiments, the recess 413 can have a lateral dimension somewhere between what is shown in FIG. 4A and the lateral dimension of the first set of stacked semiconductor devices 403.

[0030] FIG. 4B shows another configuration in which the base substrate 401 in FIG. 4B is carried by a chuck table 402 and the backside cooling unit 411 is attached to the chuck table 402. The backside cooling unit 411 is accordingly not part of the semiconductor device assembly 400 (FIG. 4A), but instead is a feature of the chuck table 402. In such embodiments, the backside cooling unit 411 can absorb heat generated by the thermal component 409 and inhibit or otherwise prevent such heat from transferring to either the second set of stacked semiconductor devices 405 or the third set of stacked semiconductor devices 406 via the base substrate 401 and the chuck table 402.

[0031] FIG. 5 is a block diagram illustrating a system that incorporates a semiconductor assembly in accordance with an embodiment of the present technology. Any one of the semiconductor devices having the features described above with reference to FIGS. 1A-4B can be incorporated into any of a myriad of larger and/or more complex systems, a representative example of which is a system 500 shown schematically in FIG. 5. The system 500 can include a processor 501, a memory 503 (e.g., SRAM, DRAM, flash, and/or other memory devices), input/output devices 505, and/or other subsystems or components 507. The semiconductor assemblies, devices, and device packages described above with reference to FIGS. 1-4 can be included in any of the elements shown in FIG. 5. The resulting system 500 can be configured to perform any of a wide variety of suitable computing, processing, storage, sensing, imaging, and/or other functions. Accordingly, representative examples of the system 500 include, without limitation, computers and/or other data processors, such as desktop computers, laptop computers, Internet appliances, hand-held devices (e.g., palm-top computers, wearable computers, cellular or mobile phones, personal digital assistants, music players, etc.), tablets, multi-processor systems, processor-based or programmable consumer electronics, network computers, and minicomputers. Additional representative examples of the system 500 include lights, cameras, vehicles, etc. With regard to these and other examples, the system 500 can be housed in a single unit or distributed over multiple interconnected units, e.g., through a communication network. The components of the system 500 can accordingly include local and/or remote memory storage devices and any of a wide variety of suitable computer-readable media.

[0032] FIG. 6 is a flowchart illustrating a method 600 for managing thermal energy in a semiconductor device assembly in accordance with an embodiment of the present technology. The method 600 starts, at block 601, by positioning a thermal component adjacent to a first set of stacked semiconductor devices of the semiconductor device assembly. At block 603, the method 600 continues by providing a temperature adjusting component relative to the thermal component and adjacent to a second set of stacked semiconductor devices of the semiconductor device assembly. At block 605, the method 600 continues by absorbing at least a portion of the thermal energy generated by the thermal component via the temperature adjusting component such that the temperature of the second set of stacked semiconductor devices remains within a desired range (e.g., an increase of not more than 1 to 5 degree Celsius).

[0033] The method 600, for example, can include transferring at least a portion of the thermal energy generated by the thermal component to the first set of stacked semiconductor devices such that the temperature of the first set of stacked semiconductor devices is increased. In some embodiments, the method 600 includes measuring a temperature of the first and/or second set(s) of stacked semiconductor devices, and in response to a change of the measured temperature adjusting a temperature of the temperature adjusting component or a temperature of the thermal component. For example, reducing the thermal energy when the temperature of the first set of stacked semiconductor devices (e.g., 103 or 403) has been at a sufficient temperature for a sufficient time to cure the curable layers or films, or when the temperature of the first and/or second set(s) of stacked semiconductor devices exceeds a corresponding threshold temperature.

[0034] In some embodiments, a method for managing thermal energy in accordance with the present technology can include (1) applying thermal energy from a separate thermal component to a first set of stacked semiconductor devices of a semiconductor device assembly; and (2) absorbing, by a temperature adjusting component of the semiconductor device assembly, at least a portion of thermal energy generated by the thermal component. By this arrangement, the portion of thermal energy can be inhibited from increasing the temperature of the second set of stacked semiconductor devices. In other words, the second set of stacked semiconductor devices can be at least partially thermally isolated from the first set of stacked semiconductor devices. In some embodiments, the method can further include measuring a temperature of the first and/or second set(s) of stacked semiconductor devices. In some embodiments, the method can further include in response to a change of the measured temperature, adjusting the temperature of the temperature adjusting component. In some embodiments, the method can further include in response to a change of the measured temperature, adjusting the temperature of the thermal component.

[0035] This disclosure is not intended to be exhaustive or to limit the present technology to the precise forms disclosed herein. Although specific embodiments are disclosed herein for illustrative purposes, various equivalent modifications are possible without deviating from the present technology, as those of ordinary skill in the relevant art will recognize. In some cases, well-known structures and functions have not been shown or described in detail to avoid unnecessarily obscuring the description of the embodiments of the present technology. Although steps of methods may be presented herein in a particular order, alternative embodiments may perform the steps in a different order. Similarly, certain aspects of the present technology disclosed in the context of particular embodiments can be combined or eliminated in other embodiments. Furthermore, while advantages associated with certain embodiments of the present technology may have been disclosed in the context of those embodiments, other embodiments can also exhibit such advantages, and not all embodiments need necessarily exhibit such advantages or other advantages disclosed herein to fall within the scope of the technology. Accordingly, the disclosure and associated technology can encompass other embodiments not expressly shown or described herein.

[0036] Throughout this disclosure, the singular terms a, an, and the include plural referents unless the context clearly indicates otherwise. Similarly, unless the word or is expressly limited to mean only a single item exclusive from the other items in reference to a list of two or more items, then the use of or in such a list is to be interpreted as including (a) any single item in the list, (b) all of the items in the list, or (c) any combination of the items in the list. Additionally, the term comprising is used throughout to mean including at least the recited feature(s) such that any greater number of the same feature and/or additional types of other features are not precluded. Reference herein to one embodiment, some embodiment, or similar formulations means that a particular feature, structure, operation, or characteristic described in connection with the embodiment can be included in at least one embodiment of the present technology. Thus, the appearances of such phrases or formulations herein are not necessarily all referring to the same embodiment. Furthermore, various particular features, structures, operations, or characteristics may be combined in any suitable manner in one or more embodiments.

[0037] From the foregoing, it will be appreciated that specific embodiments of the present technology have been described herein for purposes of illustration, but that various modifications may be made without deviating from the scope of the invention. The present technology is not limited except as by the appended claims.